Method for improving Nor Flash polycrystalline silicon etching and dielectric layer filling process window

Abstract

The invention relates to a method for lifting a Nor Flash polycrystalline silicon etching and dielectric layer filling process window, which comprises the following steps of: coating a bottom anti-reflection coating before etching a polycrystalline silicon layer, and lowering the polycrystalline silicon layer in a Nor Flash storage area by adopting an etchback process, so as to improve the Nor Flash polycrystalline silicon etching and dielectric layer filling process window, thereby improving the Nor Flash polycrystalline silicon etching and dielectric layer filling process window. And meanwhile, the height difference at the junction of the Nor Flash storage area and the peripheral area is reduced. According to the method, the bottom anti-reflection coating is coated before the polycrystalline silicon layer is etched, the polycrystalline silicon layer of the Nor Flash storage area is reduced by adopting the back-etching process, and meanwhile, the height difference of the junction of the Nor Flash storage area and the peripheral area is reduced, so that polycrystalline silicon etching residues and etching process window expansion caused by overlarge height difference during etching of the polycrystalline silicon layer can be avoided, and the yield of the Nor Flash storage area is improved. And the depth-to-width ratio between the control gates is also reduced due to the reduction of the height of the control gates (CG), and a dielectric layer filling process window is expanded.

Description

technical field [0001] The invention relates to the technical field of semiconductor manufacturing, in particular to a method for improving the process window of Nor Flash polysilicon etching and dielectric layer filling. Background technique [0002] With the continuous shrinking of the chip process node, the polysilicon (poly) gate pitch in the Nor Flash storage area is getting smaller and smaller, resulting in insufficient filling capacity of the subsequent dielectric layer, which is easy to form voids and cause failure. At the same time, because the thickness of the polysilicon layer in the storage area is thicker than that of the peripheral circuits, it is easy to leave polysilicon etching residues in the storage area. [0003] see Figure 3(a)~3(d) , Figure 3(a)~3(d) Shown is a structural schematic view of the polysilicon residue on the silicon-based substrate after the conventional polysilicon layer is etched. The Nor Flash includes a silicon-based substrate 10, a s...

AI Technical Summary

Problems solved by technology

[0007] The present invention is aimed at the conventional polysilicon layer etching, due to the existence of step height, deep depressions will be formed at the junction, resulting in the bottom anti-reflection layer (BARC) coating, in the depressions If the thickness is thicker, it is easy to etch incompletely when the subsequent polysilicon layer is etched, forming polysilicon residues, resulting in a small etching process window, and the filling capacity of the subsequent dielectric layer is insufficient, and it is easy to form voids, resulting in poor failure and other defects. Method for Flash polysilicon etching and dielectric layer filling process window

Images