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2250results about How to "Improve manufacturing yield" patented technology

System and method of maximizing integrated circuit manufacturing yield with fabrication process simulation driven layout optimization

A system and a method of maximizing the manufacturing yield of integrated circuit (“IC”) design using IC fabrication process simulation driven layout optimization is described. An IC design layout is automatically modified through formulation of a layout optimization problem utilizing the results of layout fabrication process compliance analysis tools. The modification of layout is performed adaptively and iteratively to make an IC layout less susceptible to yield issues while maintaining design rule correctness and minimal circuit performance impact.
Owner:CHEW MARKO P +1

Method of independent P and N gate length control of FET device made by sidewall image transfer technique

Disclosed is a method that forms a conductive layer on a substrate and patterns sacrificial structures above the conductive layer. Next, the invention forms sidewall spacers adjacent the sacrificial structures using a spacer material capable of undergoing dimensional change, after which the invention removes the sacrificial structures in processing that leaves the sidewall spacers in place. The invention then protects selected ones of the sidewall spacers using a sacrificial mask and leaves the other ones of the sidewall spacers unprotected. This allows the invention to selectively expose the unprotected sidewall spacers to processing that changes the size of the unprotected sidewall spacers. This causes the unprotected sidewall spacers have a different size than protected sidewall spacers. Then, the invention removes the sacrificial mask and patterns the conductive layer using the sidewall spacers as a gate conductor mask to create differently sized gate conductors on the substrate. Following this, the invention removes the sidewall spacers and forms the source, drain, and channel regions adjacent the gate conductors.
Owner:IBM CORP

Semiconductor device and method for manufacturing the same

A resistor element formed of a peel-preventive film, a recording layer made of chalcogenide, and an upper electrode film is formed on a semiconductor substrate, first and second insulation films are formed so as to cover the resistor element, a via hole for exposing the upper electrode film is formed through the first and second insulation films, and a plug for electrical connection to the upper electrode film is formed in the via hole. To form the via hole, the first insulation film made of silicon nitride is used as an etching stopper to perform dry etching on the second insulation film. Then, dry etching is performed on the first insulation film to expose the upper electrode film from the via hole.
Owner:RENESAS TECH CORP

Semiconductor-device manufacturing method

In a manufacturing method of a semiconductor device, a semiconductor substrate having a plurality of semiconductor chips formed on one of principal surfaces of the substrate is cut into the plurality of semiconductor chips through dicing. A first cutting process is formed on one of the principal surfaces of the substrate to produce two cutting grooves between two neighboring ones of the plurality of semiconductor chips, each cutting groove being adjacent to one of the neighboring ones of the plurality of semiconductor chips. A second cutting process is performed on the other of the principal surfaces of the substrate to produce a cutting groove overlapping the two cutting grooves produced by the first cutting process.
Owner:FUJITSU SEMICON LTD

Techniques for mounting a circuit board component to a circuit board

ActiveUS7084353B1Easily distinguishDifficult to readFinal product manufacturePrinted circuit aspectsSolderingEngineering
A circuit board has a layer of non-conductive material, and a set of soldering pads disposed on the layer of non-conductive material. The set of soldering pads defines a common axis that extends substantially through a midline of each soldering pad. Each soldering pad has, as measured perpendicularly through the common axis, an inner width, a first edge width and a second edge width. The inner width is longer than each of the first and second edge widths. Additionally, the first edge width is longer than the second edge width. Accordingly, the pads have less corner spaces that could otherwise, with melted solder, draw a circuit board component into an incorrect orientation which would result in incorrect mounting of the component. As a result, the component terminals tend to be drawn toward central regions of each pad for robust and reliable solder joint formation.
Owner:EMC IP HLDG CO LLC
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