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Etching method

An etching gas, dry etching technology, applied in semiconductor devices, electrical components, circuits, etc., can solve problems such as the effect of selective etching and etching

Active Publication Date: 2020-06-23
SHANGHAI HUAHONG GRACE SEMICON MFG CORP
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

[0005] The object of the present invention is to provide an etching method to solve the problem that the etching selection ratio affects the etching effect when etching a multilayer film structure

Method used

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Embodiment Construction

[0029] The etching method proposed by the present invention will be described in further detail below in conjunction with the accompanying drawings and specific embodiments. The advantages and features of the present invention will become clearer from the following description. It should be noted that all the drawings are in a very simplified form and use imprecise scales, and are only used to facilitate and clearly assist the purpose of illustrating the embodiments of the present invention. In addition, the structures shown in the drawings are often a part of the actual structure. In particular, each drawing needs to display different emphases, and sometimes uses different scales.

[0030] This embodiment provides an etching method, wherein the etching process in the etching method is dry etching, and the etching method includes:

[0031] Step 1 S10: Please refer to Figure 1~3 , providing a substrate 100, on which a control gate layer 101 and a floating gate layer 102 are...

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Abstract

The invention provides an etching method, and the etching method comprises the steps: providing a substrate, and sequentially stacking a control gate layer, a floating gate layer, a first word line and a second word line on the substrate, wherein the first word line and the second word line penetrate through the control gate layer and the floating gate layer, the first word line is located in a logic region, and the second word line is located in a memory cell region; etching the first word line with the first thickness; etching the floating gate layer in the logic region and the first word line with the second thickness so as to expose the control gate layer in the logic region; and etching the control gate layer in the logic region and the first word line with the third thickness so as to remove the control gate layer in the logic region. In the logic region etching process, the first word line with the first thickness is etched firstly, and then the first word line, the floating gate layer and the control gate layer are etched synchronously, so that etching residues caused by the low etching rate of the first word line are avoided. Therefore, the etching method can solve the problem that etching residues are generated due to etching selection ratio, the process effect is guaranteed, and the process time is saved.

Description

technical field [0001] The invention relates to the technical field of semiconductor manufacturing, in particular to an etching method. Background technique [0002] Etching selectivity refers to the etching rate ratio of one material to another material under the same etching conditions. Etching selectivity reflects that different materials are etched at different rates by the same etching gas or etching liquid. Therefore, when faced with some relatively complex multilayer film structures, due to the problem of etching selectivity in the etching process, problems such as etching not reaching expectations, etch residues or holes often occur. [0003] In the etching of the memory platform, due to the complex structure, the etching selection ratio has a great influence on the etching effect, which often causes many etching problems. Especially in the etching process of the logic area of ​​the memory, due to the limitation of the equipment, we must first remove all the film l...

Claims

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Application Information

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IPC IPC(8): H01L21/3213H01L27/11521H01L27/11531H10B41/30H10B41/42
CPCH01L21/3213H10B41/42H10B41/30
Inventor 戴鸿冉
Owner SHANGHAI HUAHONG GRACE SEMICON MFG CORP
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