793 results about "Grid pattern" patented technology

Methods of forming arrays of small, densely spaced holes or pillars for use in integrated circuits are disclosed. Various pattern transfer and etching steps can be used, in combination with pitch-reduction techniques, to create densely-packed features. Conventional photolithography steps can be used in combination with pitch-reduction techniques to form superimposed patterns of crossing elongate features with pillars at the intersections. Spacers are simultaneously applied to sidewalls of both sets of crossing lines to produce a pitch-doubled grid pattern. The pillars facilitate rows of spacers bridging columns of spacers.

A chemical vapor deposition apparatus comprises a chamber, a chamber lead having a gas in port configured to receive a reaction gas, the chamber lead connected to a top surface of the chamber to seal up the chamber, a shower head connected to the chamber lead, the shower head having a plurality of spray holes separated from each other for spraying the reaction gas onto the surface of a wafer in the chamber, and a protrusion surrounding the spray holes on the bottom surface of the shower head so that an induction groove is provided inside the protrusion, wherein the plurality of spray holes have a plurality of main holes and a plurality of supplementary holes, each of the main holes is uniformly arranged in each corner of a square-grid pattern across the shower head and each of the supplementary holes is disposed at each centerpoint of the square-grid pattern.

A digital image processing method for locating faces in a digital color image includes the steps of: generating a mean grid pattern element (MGPe) image from a plurality of sample face images; generating an integral image from the digital color image; and locating faces in the color digital image by using the integral image to perform a correlation between the mean grid pattern element (MGPe) image and the digital color image at a plurality of effective resolutions by reducing the digital color image to grid pattern element images (GPes) at different effective resolutions and correlating the MGPe with the GPes.

A method (300) for fabricating an integrated circuit includes the step of providing a substrate having a semiconductor surface (305). For at least one masking level (e.g. gate electrode, contact or via) of the integrated circuit, a mask pattern for the masking level is partitioned into a first mask and at least a second mask (310). The first mask provides features in a first grid pattern and the second mask provides features in a second grid pattern. The first and second grid pattern have respective features that interleave with one another over at least one area. A first photoresist film is applied onto the surface of the substrate (315). The first grid pattern is printed using the first mask (320). The second grid pattern is printed using the second mask (325). The first and said second grid pattern are then etched into the surface of the substrate (330). Another embodiment of the invention includes an integrated circuit (240) that has vias or contacts in a grid-like feature pattern in at least one multi-transistor area of the circuit including at least 5 transistors, wherein a minimum horizontal or minimum vertical center-to-center spacing distance between neighboring features in the pattern is ≦100 nm.

A digital image processing method for determining an orientation of a face in a digital color image generates a mean grid pattern element image from a plurality of sample face images and an integral image from the digital color image. A face is located in the color digital image by using the integral image to perform a correlation test between the mean grid pattern element image and the digital color image at a plurality of effective resolutions by reducing the digital color image to a plurality of grid pattern element images at different effective resolutions and correlating the mean grid pattern element image with the plurality of grid pattern element images, whereby either the mean grid pattern element image or the grid pattern element images are provided at a plurality of different orientations. Accordingly, an orientation of the face in the color digital image is determined by using the images with different orientations in the correlation test.

A sensing system for use in monitoring the structural health of a structure such as a polymeric matrix composite structure is provided. The system includes a sensor formed from a conductive ink containing carbon nanofibers and a polymeric resin, and a data acquisition system for acquiring and evaluating data from the sensor. The conductive ink may be applied directly to the structure to be monitored in the form of a grid pattern. Damage to the structure may be detected by measuring changes in resistance values detected from the sensor.

There are provided a lead frame including a plurality of first external terminal portions 5 provided on a plane, inner lead portions 6 formed of back surfaces of the respective first external terminal portions and arranged so as to surround a region inside the inner lead portions, and second external terminal portions 7 formed of uppermost surfaces of convex portions positioned outside the respective inner lead portions; a semiconductor element 2 flip-chip bonded to the inner lead portions via bumps 3; and an encapsulating resin 4 encapsulating surroundings of the semiconductor element and the inner lead portions. The first external terminal portions are arranged in a lower surface region of the encapsulating resin along a periphery of the region, and the second external terminal portions are exposed on an upper surface of the encapsulating resin. A plurality of terminals 8 for electrical connection are provided in a grid pattern in a region inside the first external terminal portions and exposed on a lower surface of the encapsulating resin. A plurality of semiconductor elements or coils and resistors can be incorporated, and further semiconductor devices can be stacked.

The invention provides parametric modules called Self Implementing Modules (SIMs) for use in programmable logic devices such as FPGAS. The invention further provides tools and methods for generating and using SIMs. SIMs implement themselves at the time the design is elaborated, targeting a specified FPGA according to specified parameters. In one embodiment, a SIM references or includes one or more floorplanners each of which may employ one or more placement algorithms. Such placement algorithms might include, for example: a linear ordering algorithm that places datapath logic bitwise in a regular linear pattern; a rectangular mesh algorithm that implements memory in a grid pattern in distributed RAM; a columnar algorithm for counters and other arithmetic logic; or a simulated annealing algorithm for random logic such as control logic. Therefore, a design including more than one SIM can utilize a plurality of placement algorithms at the same or different levels of hierarchy. The design as a whole can therefore utilize a non-uniform global placement strategy.

A method of applying a profiled abradable coating onto a substrate in which an abradable ceramic coating composition is applied to a metal substrate using one or more coating application techniques to produce a defined ceramic pattern without requiring a separate web or grid to be brazed onto the substrate. The invention is particularly designed to withstand the higher operating temperatures encountered with the stage 1 section of 7FA+e gas turbines to allow for increased coating life without significant deterioration in structural or functional integrity. Typically, the grid pattern coating begins approximately 0.431″ after the leading edge of the shroud, and ends approximately 1.60″ before the trailing edge of the shroud. In the case of diamond-shaped patterns, the grid pattern will be about 0.28″ long and 0.28″ wide, with an overall thickness of about 0.46.″ The coatings thus provide the required levels of abradability and leakage performance and may be applied as a chevron or diamond pattern with the shape oriented such that the diagonals run perpendicular and parallel to the sides of the shroud.

A method, system and computer program product for designating the order in which a plurality of tasks are to be executed on a computer system. In one embodiment, a plurality of task icons, each of which represents a respective one task, are shown in defined positions in a view on the computer system, and these defined positions of the task icons are used to determine the order in which the tasks are to be executed by the computer system. In an embodiment, the task icons are shown in a grid pattern, having rows and columns. Tasks represented by task icons shown in successive rows of the grid pattern are executed in series, and tasks represented by task icons shown in the same row of the grid pattern are executed in parallel. In an embodiment, at least one of the task icons represents an embedded executable workflow folder.

A leak in a membrane on top of a horizontal roof deck is located by applying conductive wires on the membrane underneath the aggregate in a grid pattern. A measuring and switching circuit generates voltage having a positive attached to the roof deck and a negative attached to the wires. The circuit has a relay for each wire which can be switched between a current sensor system and the negative potential. The sensor system is arranged to sense at each of the wires in turn the current flowing from the roof deck through any leak in the membrane to the wire. A microprocessor operates the relays in turn to connect all the other wires to the negative as a shield while each wire is sensed. From the output of the grid the changes in current in the x and y directions are analyzed to locate the leak in the membrane.

A method for forming a prograde kinematic model allowing reproduction in 3D intermediate geometries of geologic objects of an underground zone such as a sedimentary basin, from an initial state to a current state. A representation of the current geometry of the geologic objects of the zone is formed by interpretation of acquired data obtained by seismic exploration, by in-situ measurements and by observations, then each geologic object is subdivided into layers separated by deformation interfaces. Each one of the layers is defined by means of a grid pattern into a series of hexahedral volume elements. Tectonic deformations are then applied separately and successively to each series of volume elements of a layer in relation to an underlying layer while conserving the thickness and the surface area of an intermediate neutral surface in each volume element. Then the tectonic deformations are iteratively modified until a geologic representation substantially in accordance with the known final state of the underground zone is obtained.

A traceless midplane contains substantially no traces, pins, or active components and includes a front portion and a back portion. The front portion includes first connectors. The back portion includes second connectors arranged in a grid pattern. Each of the second connectors includes electrically-conductive conduits that connect the second connector to a corresponding one of the first connectors through the midplane. The second connectors include data connection points, ground connection points, and clock connection points. At least some of the data connection points are separated from each other and from the clock connection points by the ground connection points.

The invention provides parametric modules called Self Implementing Modules (SIMs) for use in programmable logic devices such as FPGAs. The invention further provides tools and methods for generating and using SIMs. SIMs implement themselves at the time the design is elaborated, targeting a specified FPGA according to specified parameters. In one embodiment, a SIM references or includes one or more floorplanners each of which may employ one or more placement algorithms. Such placement algorithms might include, for example: a linear ordering algorithm that places datapath logic bitwise in a regular linear pattern; a rectangular mesh algorithm that implements memory in a grid pattern in distributed RAM; a columnar algorithm for counters and other arithmetic logic; or a simulated annealing algorithm for random logic such as control logic. Therefore, a design including more than one SIM can utilize a plurality of placement algorithms at the same or different levels of hierarchy. The design as a whole can therefore utilize a non-uniform global placement strategy.

A method for manufacturing a composite structure is disclosed herein. The process uses a frame and selectively pressurizable forms. The forms define the interior members of the composite structure and frames define the exterior surface of the composite structure. Composite material is wrapped around the forms and the forms and composite material are placed in the frame. Selective forms are then pressurized and the composite material is co-cured together. A single piece co-cured fuselage incorporating a plurality of stiffeners is also disclosed in the application. The stiffeners are co-cured to the fuselage and may be in various patterns. The patterns may include an iso-grid pattern, and ortho-grid pattern, and a hoop-grid pattern.

A leak in a membrane on top of a horizontal roof deck is located by applying conductive wires on the membrane underneath the aggregate in a grid pattern. A measuring and switching circuit generates voltage having a positive attached to the roof deck and a negative attached to the wires. The circuit has a relay for each wire which can be switched between a current sensor system and the negative potential. The sensor system is arranged to sense at each of the wires in turn the current flowing from the roof deck through any leak in the membrane to the wire. A micro-processor operates the relays in turn to connect all the other wires to the negative as a shield while each wire is sensed. From the output of the grid the changes in current in the x and y directions are analyzed to locate the leak in the membrane.

Disclosed are embodiments of a lithographic patterning method that incorporates a combination of photolithography and self-assembling copolymer lithography techniques in order to create, on a substrate, a grid-pattern mask having multiple cells, each with at least one sub-50 nm dimension. The combination of different lithographic techniques further allows for precise registration and overlay of the individual grid-pattern cells with corresponding structures within the substrate. The resulting grid-pattern mask can then be used, in conjunction with directional etch and other processes, to extend the cell patterns into the substrate and, thereby form openings, with at least one sub-50 nm dimension, landing on corresponding in-substrate structures. Once the openings are formed, additional structures can be formed within the openings.

There are provided a lead frame including a plurality of first external terminal portions 5 provided on a plane, inner lead portions 6 formed of back surfaces of the respective first external terminal portions and arranged so as to surround a region inside the inner lead portions, and second external terminal portions 7 formed of uppermost surfaces of convex portions positioned outside the respective inner lead portions; a semiconductor element 2 flip-chip bonded to the inner lead portions via bumps 3; and an encapsulating resin 4 encapsulating surroundings of the semiconductor element and the inner lead portions. The first external terminal portions are arranged in a lower surface region of the encapsulating resin along a periphery of the region, and the second external terminal portions are exposed on an upper surface of the encapsulating resin. A plurality of terminals 8 for electrical connection are provided in a grid pattern in a region inside the first external terminal portions and exposed on a lower surface of the encapsulating resin. A plurality of semiconductor elements or coils and resistors can be incorporated, and further semiconductor devices can be stacked.

A method having application for petroleum exploration or geological storage of generating a mesh of a faulted underground medium, comprising generating a hex-dominant mesh from faults and horizons in a form of a 3D triangulated surfaces. Each 3D triangulated surface is converted to a 2D triangulated surface onto which the faults are projected by an isometric unfolding technique. A regular two-dimensional grid pattern is generated for each 2D triangulated surface. The faults are accounted for by deforming quadrilaterals of the grid pattern intersected by projected faults. The deformed regular grid pattern is then converted to a 3D gridded surface and each quadrilateral which is crossed by a fault is converted into two triangles at a level of a diagonal. Finally, after iterating for all the 3D triangulated surfaces, the mesh is generated by creating links between the nodes of neighboring three-dimensional gridded surfaces with respect to the faults.

A system and method for controlling preparation of a plurality of food items on a cooking apparatus such as a grill. A food order consisting of the plurality of food items is input to a controller which retrieves cooking times for the items from a database. A primary fire item (PFI) is determined as the item with the longest cooking time. A display screen near the cook has a surface that is laid out in a grid pattern representing the cooking surface of the grill. An icon associated with the PFI is then displayed in a position corresponding to the item's intended position on the grill. Time delays are calculated for displaying subsequent icons so that, by placing the food items on the grill when each icon is displayed, the preparation of the food items is completed simultaneously.

A pattern layout structure of package substrate includes a plurality of patterned circuit layers alternately stacking up with at least an insulative layer for isolating the patterned circuit layers wherein the patterned circuit layers are electrically connected each other. The feature of the pattern layout is that the patterned circuit layer includes a signal circuit region, a power / ground region, and a dummy circuit region. The signal circuit region includes a multiplicity of conductive traces, and the power / ground region includes a first grid-like pattern while the dummy circuit region includes a second grid-like pattern. The pitch of either the first or second grid patterns is equal to the pitch of the conductive traces.

A storage system and a load handling device for lifting and moving containers stacked in the storage system are described. The storage system includes a plurality of rails or tracks arranged in a grid pattern above the stacks of containers. The grid pattern can include a plurality of grid spaces and each stack is located within a footprint of only a single grid space. The load handling device is configured to move laterally on the rails or tracks above the stacks. The load-handling device includes a container-receiving space located above the rails or tracks in use and a lifting device arranged to lift a container from a stack into the container-receiving space. The load handling device has a footprint that, in use, occupies only a single grid space in the storage system.

A wire grid polarization film, a method for manufacturing the same, and a method for manufacturing a mold for forming grids thereof are disclosed. The wire grid polarization film comprises a substrate, a grid structure layer stacked on the substrate, and at least one metallic layer formed on one side of the grid structure layer. The method for manufacturing the wire grid polarization film comprises preparing a substrate, applying a grid structure layer to an upper surface the substrate, forming a grid pattern on the grid structure layer, and depositing a metal layer on the grid pattern. The method for manufacturing the mold comprises applying a photoresist film on a substrate, patterning the photoresist film using interference fringes via laser, developing the photoresist film, stacking a material for forming a grid pattern of the wire grid polarization film on the photoresist film, and removing the substrate and the photoresist film.

A specially designed sonotrode and anvil are adapted to be used in combination for ultrasonic welding of work pieces, to produce a narrower weld region, but one exhibiting greater durability, thereby permitting use of less packaging material. The contact surfaces comprise a surface of the anvil having a plurality of energy directors, where the plurality of energy directors are arranged into a three-dimensional grid pattern to be capable of distributed vibration-transmissive contact. The energy directors may comprise a series of plateau surfaces being regularly spaced apart from each other in a first direction, and in a second direction that is orthogonal to the first direction, to form the grid pattern. The rectangular-shaped plateaus may be spaced apart by valleys. Engagement of the energy directors of the anvil with the corresponding surface of the sonotrode may cause minor elastic deformation of work pieces positioned therebetween prior to ultrasonic welding.

It is an object of the present invention to provide a method for manufacturing a crystalline semiconductor film comprising the steps of crystallizing with the use of the metal element for promoting the crystallization to control the orientation and irradiating the laser once to form a crystalline semiconductor film having a small crystal grain arranged in a grid pattern at a regular interval.In the present invention made in view of the above object, a ridge forms a grid pattern on a surface of the crystalline semiconductor film in such a way that a crystalline semiconductor film is formed by adding the metal element for promoting the crystallization to the amorphous semiconductor film and the pulsed laser whose polarization direction is controlled is irradiated thereto. As the means for controlling the polarization direction, a half-wave plate or a mirror is used.

An optical touch panel is provided, which may comprise a rectangular position-detecting surface; a plurality of light-emitting element pairs configured for emitting a plurality of light beams; two reflectors configured for reflecting the plurality of light beams emitted by the plurality of light-emitting element pairs; and a plurality of light-receiving element pairs configured for receiving the plurality of light beams emitted by the plurality of light-emitting element pairs. The optical touch panel further may comprise a control circuit configured for causing the light-emitting element pairs to emit the plurality of light beams in a predetermined order to scan the position-detecting surface, and further configured for causing the plurality of light-receiving element pairs to receive the plurality of light beams, thereby forming optical paths on the position-detecting surface in a grid pattern. The control circuit further may be configured for determining the coordinates of an object positioned on the position-detecting surface.

The invention relates to a preparing method of a transparent electrode based on a metal nanometer grid. The method comprises the following steps that (1) photoresist coats a silicon substrate in a spin-coating way and is baked; (2) exposure and development are carried out, and the photoresist is etched into a nanometer grid pattern on the silicon substrate; (3) a metal layer is deposited on the photoresist of the nanometer grid pattern; (4) the photoresist is removed through stripping, and a metal nanometer grid formed on the silicon substrate is obtained; (5) bonding agents coat the metal nanometer grid in a spin-coating way, and in addition, a transparent substrate is adhered and cured; (6) the silicon substrate is removed through corrosion, and the transparent electrode based on the metal nanometer grid arranged on the transparent substrate is obtained. The method is simple, the implementation is easy, the integration and the large-scale production are easily realized, and the electrical conductivity and the light transmittance of the prepared transparent electrode are controllable.