69results about How to "Reduce the amount of etching" patented technology

The invention provides a plasma processing method and a modifying method of a resist pattern, which is capable of synchronously realizing excellent etching selectivity and shape performance in the process of etching fine holes with high aspect ratio on an oxidation film. The method comprises the following steps: a step of moving the oxidation film, a hard mask layer and the patterned base plate ofa photoresist, which are formed with etched objects in sequence, to a processing container (10) and loading on a lower electrode; a step of supplying a processing gas containing CxFy (wherein x is aninteger less than 3 and y is an integer less than 8), C4F8, rare gas and O2 to the processing container (10); a step of exerting a high-frequency power on an upper electrode (34) from a first high-frequency exerting unit (48) for generation of the plasmas of the processing gas; a step of exerting a high-frequency power for bias voltage on a lower electrode (16) from a second high-frequency powerexerting unit (90); and a step of exerting a direct current voltage on the upper electrode (34) from a direct current voltage exerting unit (50).

A process is described for treating metal surfaces with a composition comprising an oxidizer, an acid, a corrosion inhibitor, an unsaturated alkyl substituted with an aromatic or non-aromatic cyclic groups, and optionally but preferably a source of adhesion enhancing species selected from the group consisting of molybdates, tungstates, tantalates, niobates, vanadates, isopoly or heteropoly acids of molybdenum, tungsten, tantalum, niobium, vanadium, and combinations of any of the foregoing, an organic nitro compound, and a source of halide ions in order to increase the adhesion of polymeric materials to the metal surface.

To provide a semiconductor device capable of improving accuracy in finishing a hole in which a conductive plug right under a capacitor, and a manufacturing method of such a semiconductor device comprising the following steps: a step of forming first and second conductive plugs 32 a , 32 b in first and second holes 11 a , 11 b in a first insulating film 11; a step of forming a first opening 14 a in an oxidation preventing insulating film 14 ; a step of forming an auxiliary conductive plug 36 a in the first opening 14 a; a step of forming a capacitor Q on the auxiliary conductive plug 36 a; a step of forming third and fourth holes 41 a , 41 b in a second insulating film 41 covering the capacitor Q; a step of forming the second opening 14 b in the oxidation preventing insulating film 14 under the fourth hole 41 b; a step of forming a third conductive plug 47 a in the third hole 41 a; and a step of forming a fourth conductive plug 47 b in the third hole 41 a.

The invention provides a TFT substrate group and a manufacturing method therefor. The TFT substrate group comprises a plurality of TFT substrates and partitioning regions for partitioning the plurality of TFT substrates. The plurality of TFT substrates are provided with metal electrodes, and the interiors of the partitioning regions are provided with metal patterns, wherein the metal patterns and the metal electrodes are arranged at intervals. The metal patterns at a certain proportion are reserved in the interiors of the partitioning regions, thereby reducing the etching area, solving a problem that the etching of the edges of the metal electrodes is not complete, reducing the concentration of copper ion generated during etching, saving the use amount of etching liquid, reducing the production cost, and improving the quality of products. The method employs a shading belt with a pattern, and the shading belt cooperates with a light cover used in a conventional process of metal processing for use. The exposure, developing and etching of a metal layer are carried out, and the metal patterns separated with the metal electrodes are reserved in the partitioning regions. The method can reduce the etching amount of the metal layer in an etching process, thereby reducing the consumption of etching liquid, improving etching efficiency, and reducing the risk of incomplete etching.

A miniaturized semiconductor device is provided by reducing the design thickness of a wiring line protecting film covering the surface of a wiring layer, and reducing the distance between the wiring layer and via plugs formed by a self-aligning process. Dummy mask layers extending in the same layout pattern as the wiring layer is formed above the wiring layer covered with a protecting film composed of a cap layer and side wall layers. In the self-aligning process for forming via plugs in a self-aligned manner with the wiring layer and its protecting film, the thickness of the cap layer is reduced and the design interval between the via plugs is reduced, whereby the miniaturization of the semiconductor device is achieved.

A method of forming a wiring pattern includes forming a first conductive film pattern, an insulating film and a second conductive film pattern intersecting with the first conductive film pattern on an insulating substrate. In the method, an etching resist pattern for forming the second conductive film pattern is formed by use of a screen printing method. Thereafter, an etching resist is softened by exposing the etching resist in an organic solvent atmosphere before hardening thereof. Thus, defects such as spaces in the etching resist are repaired. By use of the above-described method of forming a wiring pattern, a TFT substrate is manufactured.