49results about How to "Reduce Interface Scattering" patented technology

The invention discloses a method for preparing an SOI (Silicon On Insulator) strain SiGe Bi CMOS (Complementary Metal-Oxide-Semiconductor) integrated device and a circuit. The preparation method comprises the steps of manufacturing an SOI bipolar transistor in bipolar device area in an SOI substrate; and conducting photoetching on an MOS (Metal Oxide Semiconductor) active region in the SOI substrate, growing strain SiGe material on the active region to respectively form NMOS (N-Channel Metal Oxide Semiconductor) active region and a PMOS (P-channel Metal Oxide Semiconductor) active region, then depositing SiO2 and polycrystalline silicon in the NMOS active region and the PMOS active region, etching a virtual gird with the length being 22-350nm, conducting self alignment to generate a source-drain region of the MOS by applying a self alignment process, removing the virtual grid, preparing a grid medium and preparing wolfram (W) to be a grid electrode, conducting photoetching on a lead wire to form the integrated device with the length being 22-350nm and the circuit of the MOS device. According to the integrated device prepared by the invention, a lightly doped source drain (LDD) structure is adopted, so that the influence on the performance of the device caused by hot carriers can be inhibited effectively; and a quantum well structure is adopted in a PMOS structure, so that a hole can be limited in a SiGe layer effectively, the interface scattering is reduced, and the electric properties of frequency, current driving capability and the like of the device are improved.

The invention provides a liquid crystal lens, comprising an upper glass substrate; a lower glass substrate; a first electrode layer arranged on the side of the upper glass substrate facing the lower glass substrate, the first electrode layer is a whole-surface conductive material; arranged on the lower glass substrate Facing the second electrode layer on the side of the upper glass substrate, the second electrode layer includes several strip electrodes and is opposite to the first electrode layer; the liquid crystal layer arranged between the first electrode layer and the second electrode layer; The thin film layer on the side of the second electrode layer facing the liquid crystal layer; also includes: a liquid crystal solidified layer arranged between the thin film layer and the second electrode layer. The present invention also provides a liquid crystal display device including the above-mentioned liquid crystal lens and a manufacturing method of the above-mentioned liquid crystal lens. The implementation of the liquid crystal lens and the liquid crystal display device provided by the embodiments of the present invention solves the problem of extra cost incurred by manufacturers in the production of liquid crystal display devices in the prior art, and reduces the phenomenon of interface scattering during light transmission.

The invention discloses a dual-strain bipolar complementary metal-oxide semiconductor (BiCMOS) integration device based on a silicon on insulator (SOI) substrate and a preparation method thereof. The preparation method comprises following steps that a negative-silicon (N-Si) layer, a positive-silicon germanium (P-SiGe) layer and an N-Si layer continuously grow on the SOI substrate, a deep groove isolator is prepared, a collector zone shallow groove isolator and a base zone shallow groove isolator are prepared, a collector zone is photo-etched, phosphonium ions are injected to form a collector electrode, a base electrode and a transmitter electrode, and a SiGe heterojunction bipolar transistor (HBT) device is formed; a strain SiGe material grow on the substrate, an N-channel MOS (NMOS) device active region and a P-channel MOS (PMOS) device active region are formed, a pseudo grid is prepared, a source drain region of the NMOS and the PMOS devices is respectively generated in a self-aligning way, the pseudo grid is eliminated, a lanthanum oxide (La2O3) material is prepared in a pressing groove at the pseudo grid to form a grid medium and metal tungsten (W) to form a grid electrode, a lead is photo-etched, and a dual-strain plane BiCMOS integration device and a circuit based on the SOI substrate are formed. According to the method, the characteristic that a hole mobility of the strain SiGe material is higher than that of the bulk-Si material is adequately utilized to prepare the dual-strain plane BiCMOS integration circuit based on the SOI substrate, so that the performance of the existing analog and digital-analog mixed integrated circuit is greatly improved.

A semiconductor device and a forming method thereof are provided. The forming method of the semiconductor device comprises the following steps: providing a substrate; forming a lamination structure covering the surface of the substrate, wherein the lamination structure includes a first stress layer disposed on the surface of the substrate, an intrinsic layer disposed on the surface of the first stress layer and a second stress layer disposed on the surface of the intrinsic layer, the lattice constant of the first stress layer is smaller than the lattice constant of the intrinsic layer, and the lattice constant of the intrinsic layer is smaller than the lattice constant of the second stress layer; forming a gate structure on the surface of the second stress layer; etching the lamination structure on the two sides of the gate structure to form grooves; and forming a third stress layer filling the grooves, wherein the lattice constant of the third stress layer is greater than the lattice constant of the first stress layer. The leakage current in the semiconductor device is reduced and the source-to-drain punch-through problem of the semiconductor device is inhibited while the carrier mobility of the semiconductor device is improved.

The invention discloses an SOI (Silicon-On-Insulator)-BJT (Bipolar Junction Transistor) double-strain-plane Bi CMOS (Complementary Metal-Oxide-Semiconductor) integrated device and a preparation method of the device. The preparation process is as follows: growing an N type Si epitaxial collector region on an SOI substrate sheet, preparing a deep-trench isolator, and manufacturing a conventional Si bipolar transistor in a bipolar device region; etching a deep trench in an active region of an MOS (Metal Oxide Semiconductor) device by utilizing a dry etching process, and respectively and selectively growing a P type Si layer, a P type SiGe gradual change layer, a P type SiGe layer, a P type strain Si layer which are taken as an active region of an NMOS (N-Channel Metal Oxide Semiconductor) device, an N type Si layer, an N type strain SiGe layer and an N type Si cap layer which are taken as an active region of a PMOS (P-Channel Metal Oxide Semiconductor) device in the trench in an epitaxial manner; and preparing a virtual grid electrode, respectively injecting LDD (Laser Detector Diode) of the MOS device, depositing SiO2, preparing a side wall, and conducting self alignment to form source drain of the NMOS device and the PMOS device; and etching a virtual grid, depositing a SiON grid dielectric layer and a W-TiN composite grid, and thus finally forming the Bi CMOS integrated device with the channel being 22-45nm. According to the method, the tensile strain Si with high electronic mobility and compressive strain SiGe with high hole mobility are respectively taken as conducting channels of the NMOS device and the PMOS device, so that the performances of the Bi CMOS integrated device and a circuit are improved greatly.

The invention discloses an SOI (silicon-on-insulator) three-strain planar BiCMOS (complementary metal oxide semiconductor) integrated device and a preparation method thereof. The method includes: growing an N-type Si epitaxial layer on an SOI substrate to serve as a collector region of a bipolar device, preparing deep grooves for isolation, and sequentially preparing base polycrystals, a base region, an emitter region and a collector to form an SiGe HBT (heterojunction bipolar transistor) device; photoetching grooves in an active region of an NMOS device, growing materials of four layers in the grooves, and preparing a gate dielectric layer and gate polycrystals in the active region of the NMOS device to form the NMOS device; photoetching grooves in an active region of a PMOS device, growing materials of five layers in the grooves, and preparing a drain and a grid on the active region of the PMOS device to form the PMOS device; and photoetching leads to form the SOI three-strain planar BiCMOS integrated device and circuits. The emitter, the base and the collector of the SiGe HBT device are all polycrystals which can be partially made on an oxide layer to reduce the active region area of the device, and accordingly the size of the device is reduced, the integration level of the circuits is increased, and performances of the SOI three-strain planar BiCMOS integrated circuits are enhanced.