Double-strain plane BiCMOS (Bipolar Complementary Metal-Oxide-Semiconductor Transistor) integrated device and preparation method
An integrated device, double-strain technology, applied in semiconductor/solid-state device manufacturing, electric solid-state devices, semiconductor devices, etc., can solve the problems of confinement, low carrier material mobility of Si materials, etc.
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Embodiment 1
[0096] Embodiment 1: preparation of a dual-strained plane BiCMOS integrated device and circuit with a conduction channel of 45nm,
[0097] Specific steps are as follows:
[0098] Step 1, epitaxial growth.
[0099] (1a) Select the doping concentration to be 5×10 14 cm -3 A P-type Si sheet as a substrate;
[0100] (1b) Thermally oxidize a layer of SiO with a thickness of 300nm on the substrate surface 2 layer;
[0101] (1c) Photoetching the buried layer region, implanting N-type impurities into the buried layer region, and annealing at 800° C. for 90 minutes to activate the impurities to form an N-type heavily doped buried layer region.
[0102] Step 2, isolation area preparation.
[0103] (2a) Remove the excess oxide layer on the surface, and epitaxially grow a layer with a doping concentration of 1×10 16 cm -3 The Si layer, with a thickness of 2 μm, serves as the collector area;
[0104] (2b) Thermally oxidize a layer of SiO with a thickness of 300nm on the substrate ...
Embodiment 2
[0147] Embodiment 2: Preparation of a dual-strained plane BiCMOS integrated device and circuit with a conductive channel of 30nm,
[0148] Specific steps are as follows:
[0149] Step 1, epitaxial growth.
[0150] (1a) Select the doping concentration as 1×10 15 cm -3 A P-type Si sheet as a substrate;
[0151] (1b) Thermally oxidize a layer of SiO with a thickness of 400nm on the substrate surface 2 layer;
[0152] (1c) Photoetching the buried layer region, implanting N-type impurities into the buried layer region, and annealing at 900° C. for 60 minutes to activate the impurities to form an N-type heavily doped buried layer region.
[0153] Step 2, isolation area preparation.
[0154] (2a) Remove the excess oxide layer on the surface, and epitaxially grow a layer with a doping concentration of 5×10 16 cm -3 A Si layer with a thickness of 2.5 μm acts as a collector area;
[0155] (2b) Thermally oxidize a layer of SiO with a thickness of 400nm on the surface of the subs...
Embodiment 3
[0198] Embodiment 3: preparation of a dual-strained plane BiCMOS integrated device and circuit with a conductive channel of 22nm,
[0199] Specific steps are as follows:
[0200] Step 1, epitaxial growth.
[0201] (1a) Select the doping concentration to be 5×10 15 cm -3 A P-type Si sheet as a substrate;
[0202] (1b) Thermally oxidize a layer of SiO with a thickness of 500nm on the surface of the substrate 2 layer;
[0203] (1c) Photoetching the buried layer region, implanting N-type impurities into the buried layer region, and annealing at 950° C. for 30 minutes to activate the impurities to form an N-type heavily doped buried layer region.
[0204] Step 2, isolation area preparation.
[0205] (2a) Remove the excess oxide layer on the surface, and epitaxially grow a layer with a doping concentration of 1×10 17 cm -3 The Si layer, with a thickness of 3 μm, serves as the collector area;
[0206] (2b) Thermally oxidize a layer of SiO with a thickness of 500nm on the sub...
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