70 results about "Bicmos technology" patented technology

A method and a BICMOS structure are provided. The BiCMOS structure includes an SOI substrate having a bottom Si-containing layer, a buried insulating layer located atop the bottom Si-containing layer, a top Si-containing layer atop the buried insulating layer and a sub-collector which is located in an upper surface of the bottom Si-containing layer. The sub-collector is in contact with a bottom surface of the buried insulating layer. The structure also includes an extrinsic base heterojunction bipolar transistor located in an opening provided in a bipolar device area of the SOI substrate in which a base region of the bipolar transistor is located directly atop the sub-collector

A method and structure for a bipolar transistor comprising a patterned isolation region formed below an upper surface of a semiconductor substrate and a single crystal extrinsic base formed on an upper surface of the isolation region. The single crystal extrinsic base comprises a portion of the semiconductor substrate located between the upper surface of the isolation region and the upper surface of the semiconductor substrate. The bipolar transistor further comprises a single crystal intrinsic base, wherein a portion of the single crystal extrinsic base merges with a portion of the single crystal intrinsic base. The isolation region electrically isolates the extrinsic base from a collector. The intrinsic and extrinsic bases separate the collector from an emitter. The extrinsic base comprises epitaxially-grown silicon. The isolation region comprises an insulator, which comprises oxide, and the isolation region comprises any of a shallow trench isolation region and a deep trench isolation region.

A bandgap voltage reference and voltage regulator system includes a bandgap voltage reference circuit and a voltage regulator circuit that share a single, common amplifier. The amplifier acts as a gain stage for the reference circuit and as an error amplifier for a driver stage of the regulator circuit. The regulator circuit has an input reference generated by the reference circuit, and the reference circuit acts as a load to the driver stage, obviating the need for a bias resistance network. By sharing the amplifier and obviating the need for a resistance network, the area and overall quiescent current of the system are reduced. The system can be implemented in CMOS/BiCMOS technology and is suited for low power applications.

A phased-array receiver is adapted so as to be fully integrated and fabricated on a single silicon substrate. The phased-array receiver is operative to receive a 24 GHz signal and may be adapted to include 8-elements formed in a SiGe BiCMOS technology. The phased-array receiver utilizes a heterodyne topology, and the signal combining is performed at an IF of 4.8 GHz. The phase-shifting with 4 bits of resolution is realized at the LO port of the first down-conversion mixer. A ring LC VCO generates 16 different phases of the LO. An integrated 19.2 GHz frequency synthesizer locks the VCO frequency to a 75 MHz external reference. Each signal path achieves a gain of 43 dB, a noise figure of 7.4 dB, and an IIP3 of −11 dBm. The 8-path array achieves an array gain of 61 dB, a peak-to-null ratio of 20 dB, and improves the signal-to-noise ratio at the output by 9 dB.

The invention discloses a silicone substrate high-linearity low-phase-shift ultra-broad-band digital attenuator which comprises a 1dB attenuating module, a 2dB attenuating module, a 4dB attenuating module, a 8dB attenuating module and a 16dB attenuating module. Two NMOS field effect transistors which are of a channel parallel-connection resistor structure and of a solid suspension structure and manufactured through SiGe BiCMOS technology are adopted to be used as control switches, five sets of complementary digital signals are used for controlling the five attenuating modules independently to work, a low-pass network is used for conducting phase compensation, inductance is used for matching between the adjacent attenuating modules, matching between the input end of the1dB attenuating module and 50 omega input impedance and matching between the output end of the 16dB attenuating module and 50 omega output impedance are realized through transmission wires, the working frequency range is 1-25GHz, and low-differential-loss low-phase-shift attenuation of signal amplitudes under 32 states can be realized with the 1dB length stepping in the attenuating range of 0-31dB. The silicone substrate high-linearity low-phase-shift ultra-broad-band digital attenuator has the advantages of being low in differential loss, low in accessory phase shift, high in linearity, low in production cost and low in chip area, and can be used for large-amplitude signal processing and single chip integration.

A R2R ladder circuit implementation of a digital-to-analog convertor (DAC) may be configured to compensate for mismatch in each of a plurality of current sources in the R2R ladder circuit. The compensating of mismatch in each of the plurality of current sources may be achieved by adding one or more auxiliary current sources associated with each of the plurality of current sources, which may be used to provide pre-configured auxiliary current that would enable compensating for mismatch in current of an associated one of the plurality of current sources. For example, each of the plurality of current sources may have two auxiliary current sources, connected in parallel therewith, with one of two auxiliary current sources being switched to the positive-side and the other auxiliary current source being switched to the negative-side. The switching structure of the modified R2R ladder circuit may be implemented in any semiconductor technology (e.g., BiCMOS technology).

The present invention details fabrication guidelines of integrated optoelectronic oscillators with frequency and phase stability, having higher frequency selectivity in a relatively small size (compared to the larger size of a higher order electrically realized RF filter), reduced temperature sensitivity, and minimized frequency drift. The integrated photonic components and RF oscillator may use Silicon photonics and microelectronic integration using CMOS and BiCMOS technology, eliminating the need for bulky and/or discrete optical and microwave components.

A high-frequency noise isolation structure and a method for forming the same are provided. The noise isolation structure isolates a first device region and a second device region over a semiconductor substrate. The noise isolation structure preferably includes a sinker region substantially encircling a first device region, a buried layer underlying the first device region and joining the sinker region, a deep guard ring substantially encircling the sinker region, and a deep trench oxide region substantially encircling the sinker region. The isolation structure further includes a wide guard ring between the first and the second device regions. The sinker region and the buried region preferably have a high impurity concentration. Integrated circuits to be noise decoupled are preferably formed in the respective first and second device regions.

The present invention discloses a PNP bipolar transistor in a SiGe BiCMOS (Bipolar Complementary Metal Oxide Semiconductor) technology, an active region of the bipolar transistor is isolated by making use of shallow groove field oxide layers and comprises a collector region, a base region and an emitter region, wherein the collector region is formed by a P-type buried layer located at the bottom of the shallow groove, and led out by making a deep trap contact on the field oxide layers; the base region is formed by N-type ion implantation in the active region, peripheral sides of the base region are the shallow groove field oxide layers, width of the base region is equal to depth of the shallow groove, and the bottom of the base region is connected with the collector region; an N-type buried layer is formed at the bottom of the shallow groove located at the opposite side of the collector region, the base region is connected with the N-type buried layer and led out by making the deep trap contact on the field oxide layer on the N-type buried layer; and the emitter region is formed by a P-type ion implantation layer formed above the base region or by further providing a P-type polycrystalline silicon. The PNP bipolar transistor in the present invention can reduce area of the PNP transistor and raise current amplification factor of the PNP transistor.

A heterobipolar transistor (HBT) for high-speed BiCMOS applications is provided in which the collector resistance, Rc, is lowered by providing a buried refractory metal silicide layer underneath the shallow trench isolation region on the subcollector of the device. Specifically, the HBT of the present invention includes a substrate including at least a subcollector; a buried refractory metal silicide layer located on the subcollector; and a shallow trench isolation region located on a surface of the buried refractory metal silicide layer. The present invention also provides a method of fabricating such a HBT. The method includes forming a buried refractory metal silicide underneath the shallow trench isolation region on the subcollector of the device.