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A kind of soi strain sige BiCMOS integrated device and preparation method

A technology for integrating devices and devices, applied in the field of SOI strained SiGeBiCMOS integrated devices and preparation, can solve problems such as affecting device performance, reducing lithography accuracy, and insufficiency of lithography technology.

Inactive Publication Date: 2016-05-25
XIDIAN UNIV
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

[0004] However, with the continuous development of integrated circuit technology, the feature size of the chip continues to shrink. In the miniaturization process of the Si chip manufacturing industry, it is faced with the challenges of material physical properties, manufacturing process technology, device structure, etc.; for example, when the feature size is smaller than Due to problems such as tunneling leakage current and reliability when it is below 100nm, the traditional gate dielectric material SiO 2 Unable to meet the requirements of low power consumption; the short channel effect and narrow channel effect of nanometer devices are becoming more and more obvious, which seriously affects the device performance; traditional lithography technology cannot meet the shrinking lithography precision
Therefore, traditional Si-based process devices are increasingly difficult to meet the needs of design

Method used

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  • A kind of soi strain sige BiCMOS integrated device and preparation method

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Effect test

Embodiment 1

[0093] Embodiment 1: To prepare an SOI strained SiGeBiCMOS integrated device and circuit with a channel length of 22nm, the specific steps are as follows:

[0094] Step 1, SOI substrate material preparation.

[0095] (1a) Select the N-type doping concentration as 1×10 15 cm -3 The Si sheet is oxidized on its surface, and the thickness of the oxide layer is 1 μm, which is used as the base material of the upper layer, and hydrogen is injected into the base material;

[0096] (1b) Select the P-type doping concentration as 1×10 15 cm -3 The Si sheet is oxidized on its surface, and the thickness of the oxide layer is 1 μm, which is used as the base material of the lower layer;

[0097] (1c) Using a chemical mechanical polishing (CMP) process to polish the surface of the lower layer and the upper layer of substrate material after hydrogen injection;

[0098] (1d) Put the oxide layer on the surface of the polished lower layer and the upper layer of the base material relatively c...

Embodiment 2

[0143] Embodiment 2: To prepare an SOI strained SiGeBiCMOS integrated device and circuit with a channel length of 130nm, the specific steps are as follows:

[0144] Step 1, SOI substrate material preparation.

[0145] (1a) Select the N-type doping concentration as 3×10 15 cm -3 The Si sheet is oxidized on its surface, and the thickness of the oxide layer is 0.7 μm, which is used as the base material of the upper layer, and hydrogen is injected into the base material;

[0146] (1b) Select the P-type doping concentration as 3×10 15 cm -3 The Si sheet is oxidized on its surface, and the thickness of the oxide layer is 0.7 μm, which is used as the base material of the lower layer;

[0147] (1c) Using a chemical mechanical polishing (CMP) process to polish the surface of the lower layer and the upper layer of substrate material after hydrogen injection;

[0148] (1d) Put the oxide layer on the surface of the polished lower layer and the upper layer of the base material relativ...

Embodiment 3

[0193]Embodiment 3: The preparation of SOI strained SiGeBiCMOS integrated device and circuit with a channel length of 350nm, the specific steps are as follows:

[0194] Step 1, SOI substrate material preparation.

[0195] (1a) Select the N-type doping concentration as 5×10 15 cm -3 The Si sheet is oxidized on its surface, and the thickness of the oxide layer is 0.5 μm, which is used as the base material of the upper layer, and hydrogen is injected into the base material;

[0196] (1b) Select the P-type doping concentration as 5×10 15 cm -3 The Si sheet is oxidized on its surface, and the thickness of the oxide layer is 0.5 μm, which is used as the base material of the lower layer;

[0197] (1c) Using a chemical mechanical polishing (CMP) process to polish the surface of the substrate material of the lower layer and the upper layer of the active layer after injecting hydrogen, respectively;

[0198] (1d) Put the oxide layer on the surface of the polished lower layer and th...

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Abstract

The invention discloses a method for preparing an SOI (Silicon On Insulator) strain SiGe Bi CMOS (Complementary Metal-Oxide-Semiconductor) integrated device and a circuit. The preparation method comprises the steps of manufacturing an SOI bipolar transistor in bipolar device area in an SOI substrate; and conducting photoetching on an MOS (Metal Oxide Semiconductor) active region in the SOI substrate, growing strain SiGe material on the active region to respectively form NMOS (N-Channel Metal Oxide Semiconductor) active region and a PMOS (P-channel Metal Oxide Semiconductor) active region, then depositing SiO2 and polycrystalline silicon in the NMOS active region and the PMOS active region, etching a virtual gird with the length being 22-350nm, conducting self alignment to generate a source-drain region of the MOS by applying a self alignment process, removing the virtual grid, preparing a grid medium and preparing wolfram (W) to be a grid electrode, conducting photoetching on a lead wire to form the integrated device with the length being 22-350nm and the circuit of the MOS device. According to the integrated device prepared by the invention, a lightly doped source drain (LDD) structure is adopted, so that the influence on the performance of the device caused by hot carriers can be inhibited effectively; and a quantum well structure is adopted in a PMOS structure, so that a hole can be limited in a SiGe layer effectively, the interface scattering is reduced, and the electric properties of frequency, current driving capability and the like of the device are improved.

Description

technical field [0001] The invention belongs to the technical field of semiconductor integrated circuits, in particular to an SOI strained SiGeBiCMOS integrated device and a preparation method. Background technique [0002] Semiconductor integrated circuit technology is the core technology of high-tech and information industry, and has become an important symbol to measure a country's scientific and technological level, comprehensive national strength and national defense strength, while microelectronic technology represented by integrated circuits is the key to semiconductor technology; Industry is the basic industry of the country. The reason why it develops so fast is not only the huge contribution of technology itself to economic development, but also its wide applicability. [0003] Gordon Moore, one of the founders of Intel (Intel), proposed "Moore's Law" in 1965, which states that the number of transistors on an integrated circuit chip doubles about every 18 months, a...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): H01L27/12H01L21/84
Inventor 胡辉勇宋建军李妤晨张鹤鸣宣荣喜舒斌戴显英郝跃
Owner XIDIAN UNIV
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