A kind of soi strain sige BiCMOS integrated device and preparation method
A technology for integrating devices and devices, applied in the field of SOI strained SiGeBiCMOS integrated devices and preparation, can solve problems such as affecting device performance, reducing lithography accuracy, and insufficiency of lithography technology.
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Embodiment 1
[0093] Embodiment 1: To prepare an SOI strained SiGeBiCMOS integrated device and circuit with a channel length of 22nm, the specific steps are as follows:
[0094] Step 1, SOI substrate material preparation.
[0095] (1a) Select the N-type doping concentration as 1×10 15 cm -3 The Si sheet is oxidized on its surface, and the thickness of the oxide layer is 1 μm, which is used as the base material of the upper layer, and hydrogen is injected into the base material;
[0096] (1b) Select the P-type doping concentration as 1×10 15 cm -3 The Si sheet is oxidized on its surface, and the thickness of the oxide layer is 1 μm, which is used as the base material of the lower layer;
[0097] (1c) Using a chemical mechanical polishing (CMP) process to polish the surface of the lower layer and the upper layer of substrate material after hydrogen injection;
[0098] (1d) Put the oxide layer on the surface of the polished lower layer and the upper layer of the base material relatively c...
Embodiment 2
[0143] Embodiment 2: To prepare an SOI strained SiGeBiCMOS integrated device and circuit with a channel length of 130nm, the specific steps are as follows:
[0144] Step 1, SOI substrate material preparation.
[0145] (1a) Select the N-type doping concentration as 3×10 15 cm -3 The Si sheet is oxidized on its surface, and the thickness of the oxide layer is 0.7 μm, which is used as the base material of the upper layer, and hydrogen is injected into the base material;
[0146] (1b) Select the P-type doping concentration as 3×10 15 cm -3 The Si sheet is oxidized on its surface, and the thickness of the oxide layer is 0.7 μm, which is used as the base material of the lower layer;
[0147] (1c) Using a chemical mechanical polishing (CMP) process to polish the surface of the lower layer and the upper layer of substrate material after hydrogen injection;
[0148] (1d) Put the oxide layer on the surface of the polished lower layer and the upper layer of the base material relativ...
Embodiment 3
[0193]Embodiment 3: The preparation of SOI strained SiGeBiCMOS integrated device and circuit with a channel length of 350nm, the specific steps are as follows:
[0194] Step 1, SOI substrate material preparation.
[0195] (1a) Select the N-type doping concentration as 5×10 15 cm -3 The Si sheet is oxidized on its surface, and the thickness of the oxide layer is 0.5 μm, which is used as the base material of the upper layer, and hydrogen is injected into the base material;
[0196] (1b) Select the P-type doping concentration as 5×10 15 cm -3 The Si sheet is oxidized on its surface, and the thickness of the oxide layer is 0.5 μm, which is used as the base material of the lower layer;
[0197] (1c) Using a chemical mechanical polishing (CMP) process to polish the surface of the substrate material of the lower layer and the upper layer of the active layer after injecting hydrogen, respectively;
[0198] (1d) Put the oxide layer on the surface of the polished lower layer and th...
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