A kind of soi three-strain plane bicmos integrated device and its preparation method
An integrated device, three-strain technology, applied in semiconductor/solid-state device manufacturing, electric solid-state devices, semiconductor devices, etc., can solve problems such as low mobility and limitation of Si material carrier materials
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Embodiment 1
[0119] Embodiment 1: The SOI triple-strained plane BiCMOS integrated device and circuit with a channel length of 22nm are prepared, and the specific steps are as follows:
[0120] Step 1, epitaxial growth.
[0121] (1a) Select the SOI substrate, the support material of the lower layer of the substrate is Si, and the middle layer is SiO 2 , with a thickness of 150nm, and the upper material is doped with a concentration of 1×10 16 cm -3 N-type Si with a thickness of 100nm;
[0122] (1b) Using the chemical vapor deposition (CVD) method, at 600 ° C, grow a layer of N-type epitaxial Si layer with a thickness of 50 nm on the upper Si material, as the collector region, and the doping concentration of this layer is 1× 10 16 cm -3 .
[0123] Step 2, deep trench isolation preparation.
[0124] (2a) Deposit a layer of SiO on the surface of the substrate at 600°C by chemical vapor deposition (CVD) 2 ;
[0125] (2b) In the photolithographic isolation area, a deep groove with a dep...
Embodiment 2
[0184] Embodiment 2: The SOI triple-strained plane BiCMOS integrated device and circuit with a channel length of 30nm are prepared, and the specific steps are as follows:
[0185] Step 1, epitaxial growth.
[0186] (1a) Select the SOI substrate, the support material of the lower layer of the substrate is Si, and the middle layer is SiO 2 , with a thickness of 300nm, and the upper material is doped with a concentration of 5×10 16 cm -3 N-type Si with a thickness of 120nm;
[0187] (1b) Using chemical vapor deposition (CVD), grow an N-type epitaxial Si layer with a thickness of 80nm on the upper Si material at 700°C as the collector region, and the doping concentration of this layer is 5× 10 16 cm -3 .
[0188] Step 2, deep trench isolation preparation.
[0189] (2a) Deposit a layer of SiO on the surface of the substrate at 700°C by chemical vapor deposition (CVD) 2 ;
[0190] (2b) In the photolithographic isolation area, a deep groove with a depth of 3 μm is etched in ...
Embodiment 3
[0249] Embodiment 3: The SOI triple-strained plane BiCMOS integrated device and circuit with a channel length of 45nm are prepared, and the specific steps are as follows:
[0250] Step 1, epitaxial growth.
[0251] (1a) Select the SOI substrate, the support material of the lower layer of the substrate is Si, and the middle layer is SiO 2 , with a thickness of 400nm, and the upper material is doped with a concentration of 1×10 17 cm -3 N-type Si with a thickness of 150nm;
[0252] (1b) Using the method of chemical vapor deposition (CVD), grow a layer of N-type epitaxial Si layer with a thickness of 100nm on the upper layer of Si material at 750°C, as the collector region, and the doping concentration of this layer is 1× 10 17 cm -3 .
[0253] Step 2, deep trench isolation preparation.
[0254] (2a) Deposit a layer of SiO on the surface of the substrate at 800°C by chemical vapor deposition (CVD) 2 ;
[0255] (2b) In the photolithographic isolation area, a deep groove w...
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