Silicon on insulator (SOI) SiGe bipolar complementary metal oxide semiconductor (BiCMOS) integrated device and preparation method thereof
An integrated device and device technology, which is applied in the preparation of SOI SiGe BiCMOS integrated devices and the field of preparation, can solve problems such as affecting device performance, difficult to meet design, and inability to meet low power consumption and other problems
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Embodiment 1
[0120] Embodiment 1: the preparation channel length is the SOI SiGe BiCMOS integrated device and the circuit of 22nm, concrete steps are as follows:
[0121] Step 1, epitaxial growth.
[0122] (1a) Select the SOI substrate, the support material of the lower layer of the substrate is Si, and the middle layer is SiO 2 , with a thickness of 150nm, and the upper material is doped with a concentration of 1×10 16 cm -3 N-type Si with a thickness of 100nm;
[0123] (1b) Using chemical vapor deposition (CVD), grow a layer of N-type epitaxial Si layer with a thickness of 50nm on the upper Si material at 600°C, as the collector region, and the doping concentration of this layer is 1× 10 16 cm -3 .
[0124] Step 2, shallow trench isolation preparation.
[0125] (2a) Using chemical vapor deposition (CVD), grow a layer of SiO with a thickness of 300 nm on the surface of the epitaxial Si layer at 600 °C. 2 Floor;
[0126] (2b) Photolithographic shallow trench isolation area;
[0...
Embodiment 2
[0183] Embodiment 2: the preparation channel length is the SOI SiGe BiCMOS integrated device and the circuit of 130nm, and concrete steps are as follows:
[0184] Step 1, epitaxial growth.
[0185] (1a) Select the SOI substrate, the support material of the lower layer of the substrate is Si, and the middle layer is SiO 2 , with a thickness of 300nm, and the upper material is doped with a concentration of 5×10 16 cm -3 N-type Si with a thickness of 120nm;
[0186](1b) Using chemical vapor deposition (CVD), grow an N-type epitaxial Si layer with a thickness of 80nm on the upper Si material at 700°C as the collector region, and the doping concentration of this layer is 5× 10 16 cm -3 .
[0187] Step 2, shallow trench isolation preparation.
[0188] (2a) Using chemical vapor deposition (CVD), grow a layer of SiO with a thickness of 400 nm on the surface of the epitaxial Si layer at 700 °C. 2 Floor;
[0189] (2b) Photolithographic shallow trench isolation area;
[0190] ...
Embodiment 3
[0246] Embodiment 3: the preparation channel length is the SOI SiGe BiCMOS integrated device and the circuit of 350nm, and concrete steps are as follows:
[0247] Step 1, epitaxial growth.
[0248] (1a) Select the SOI substrate, the support material of the lower layer of the substrate is Si, and the middle layer is SiO 2 , with a thickness of 400nm, and the upper material is doped with a concentration of 1×10 17 cm -3 N-type Si with a thickness of 150nm;
[0249] (1b) Using the method of chemical vapor deposition (CVD), grow a layer of N-type epitaxial Si layer with a thickness of 100nm on the upper layer of Si material at 750°C, as the collector region, and the doping concentration of this layer is 1× 10 17 cm -3 .
[0250] Step 2, shallow trench isolation preparation.
[0251] (2a) Using chemical vapor deposition (CVD), grow a layer of SiO with a thickness of 500 nm on the surface of the epitaxial Si layer at 800 °C. 2 Floor;
[0252] (2b) Photolithographic shallow...
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