59results about How to "Reduce etch depth" patented technology

A surface-emitting laser array includes a plurality of surface-emitting laser elements. Each surface-emitting laser element includes a first reflection layer formed on a substrate, a resonator formed in contact with the first reflection layer and containing an active layer, and a second reflection layer formed over the first reflection layer and in contact with the resonator. The second reflection layer contains a selective oxidation layer. The first reflection layer contains on the active layer side at least a low refractive index layer having an oxidation rate equivalent to or larger than an oxidation rate of a selective oxidation layer contained in the second reflection layer. The resonator is made of an AlGaInPAs base material containing at least In. A bottom of a mesa structure is located under the selective oxidation layer and over the first reflection layer.

The present invention includes an optical waveguide with a grating and a method of making the same for increasing the effectiveness of the grating. In one example, the grating is at least partially covered by a liner layer disposed on at least a portion of a grating; and a cover layer disposed on the liner layer, wherein a first material selected for the core and ridges and a second material selected for the liner layer are selected to provide a difference in the index of refraction between the first and second material that is sufficient to provide a contrast therebetween.

The invention provides a cavity type bulk acoustic wave resonator with a support column and a preparation method of the cavity type bulk acoustic wave resonator. The method comprises the following steps of: taking a piezoelectric single crystal wafer which is subjected to ion implantation and is provided with a bottom electrode; forming a plurality of supporting columns on one side, with the bottom electrode, of the piezoelectric single crystal wafer; forming a cavity at the gap of supporting columns, taking the substrate, bonding the substrate with one side of the piezoelectric single crystalwafer with the cavity, carrying out heat treatment on the substrate after bonding, stripping a film of the piezoelectric single crystal wafer, and producing a top electrode on the stripped side of the piezoelectric single crystal wafer to obtain the piezoelectric single crystal wafer. According to the technical scheme provided by the invention, a sacrificial layer does not need to be grown, etching and trepanning are not carried out on the thin film, the mechanical strength of the device is improved, and the thin film is not easily damaged; the cavity structure is formed before film formation, the rate of finished products is high, residues left by etching after film formation do not exist, and the influence of incomplete release on the device does not need to be considered.

The invention relates to a treatment method of an aluminium foil bionic nanostructured super-hydrophobic anti-condensation functional surface. The method comprises the following steps: firstly performing ultrasonic cleaning of an aluminium foil with acetone and deionized water, blowing to dry, soaking the aluminium foil into a 1 mol/L NaOH aqueous solution for treatment for 30-60 s, cleaning with ethanol and deionized water in order, blowing to dry so as to keep in reserve; soaking the pretreated aluminium foil in liquid which adopts a mixed aqueous solution of phosphoric acid and glycerol as an electrolyte, performing anodization under a room-temperature condition in a constant current density mode for 120-150 min; after the anodization is completed, taking the aluminium foil out, cleaning with ethanol and deionized water, blowing to dry; soaking the anodized aluminium foil in liquid stearic acid at 70 DEG C for 1 h, rinsing in hot ethanol with a temperature of 70 DEG C, curing in an oven with a temperature of 80 DEG C for 30 min so as to prepare the aluminium foil bionic nanostructured super-hydrophobic anti-condensation functional surface. The invention has a simple preparation process, no pollution, less substrate damage, excellent surface quality, and is applicable to popularization and application.

The invention discloses high anti-dazzle glass and a preparing technology. An etchant layer with the depth of 0.10 micron to 0.20 micron is arranged on the surface of glass, and comprises compact, regular and honeycomb hexagon etched patterns. The preparing technology includes the following steps of 1, cleaning , wherein the surface of the glass is cleaned with water or deionized water; 2, etching, wherein etching liquid is sprayed to the surface of the glass with the spraying method, and comprises, by weight, 35-45 parts of ammonium bifluoride, 4-15 parts of ammonium sulfate, 5-10 parts of ammonium nitrate, 5-10 parts of barium sulfate, 4-8 parts of potassium sulfate, 60-100 parts of hydrochloric acid and 20-40 parts of water; 4, polishing, wherein the etched surface of the glass is polished through mixed acid liquid of hydrofluoric acid and sulfuric acid. The reflective rate of the high anti-dazzle glass prepared with the technology is smaller than or equal to 3%, the light transmittance is larger than or equal to 90%, the roughness degree is as low as 0.15 micron or below.

A method for fabricating optoelectronic semiconductor chips and optoelectronic semiconductor chips are disclosed. In embodiments the method comprises depositing a semiconductor layer sequence having an active, the active region being arranged between a first semiconductor layer and a second semiconductor layer on a growth substrate, attaching the semiconductor layer sequence to a carrier and forming a plurality of recesses extending through the carrier, the second semiconductor layer and the active region into the first semiconductor layer. The method further comprises forming first contacts on a first main surface of the carrier, the first main surface facing away from the semiconductor layer sequence, wherein the first contacts are electrically conductively connected to the first semiconductor layer in the region of the recesses and singulating the carrier and the semiconductor layer sequence into the plurality of optoelectronic semiconductor chips, wherein each semiconductor chip has at least one recess.

Disclosed are a semiconductor structure and a formation method thereof. The semiconductor structure comprises a semiconductor substrate, a plurality of CMOS (complementary metal oxide semiconductor) devices, a first medium layer, a first interconnection structure, a through hole, an isolation layer, a second metal interconnection layer, a second medium layer and a plurality of passive devices. The semiconductor substrate comprises a first surface and a second surface, the CMOS devices are arranged on the first surface, the first medium layer covers the first surface and the CMOS device, the first interconnection structure is arranged in the first medium layer and connected with the CMOS devices, the through hole penetrates through the second surface of the semiconductor substrate and a part of the first medium layer, and the surface of the bottom of the first interconnection structure is exposed at the bottom of the through hole; the isolation layer is arranged on the side wall of the through hole and the second surface; the second metal interconnection layer is arranged on the isolation layer and at the bottom of the through hole and is connected with the surface of the bottom of the first interconnection structure; the second medium layer covers the second metal interconnection layer, and the through hole is filled with the second medium layer; the passive devices are arranged on the second medium layer, and one end of each passive device is connected with the second metal interconnection layer. The semiconductor structure is small in occupation space and high in integrity.

The invention provides a three-dimensional memory manufacturing method and a three-dimensional memory, and the method comprises: forming a semiconductor structure, and enabling a stack structure of the semiconductor structure to be provided with a first structural hole with the bottom located at an etching stop layer; removing the etching stop layer at the bottom of the first structure hole, and exposing the insulating layer at the bottom of the etching stop layer; further extending the bottom of the first structure hole into the sacrificial layer; removing the sacrificial layer to form a sacrificial gap; forming a second substrate in the sacrificial gap; and forming a common source contact in the first structural hole. An etching stop layer is arranged in a stack structure of the three-dimensional memory, the etching stop layer can be used as a stop layer for etching the first structural hole, and the etching depth in the last process step can be reduced due to the fact that the position of the etching stop layer in the stack structure is determined, so that the machining error is reduced, the etching precision is accurately controlled, and the bottom of the first structural holecan be just located in the sacrificial layer and cannot be too deep or too shallow.

The invention relates to a field effect transistor structure, a manufacturing method thereof and a chip device. A transistor comprises a drain electrode epitaxial layer located at the bottom, a source electrode layer located at the top, and a source electrode extension inverted fin and a grid electrode which are embedded in the drain electrode epitaxial layer. The grid electrode is arranged between the source electrode extension inverted fins, and symmetrical channels which are connected in parallel from the source electrode layer to the interior of the drain electrode epitaxial layer in pairs are formed in the two sides of the grid electrode. In a preferable example, paired symmetrical field resistors which are connected in parallel from the source electrode layer to the drain electrode epitaxial layer are also formed above the channels at the two sides of the grid electrode; in a preferable example, the drain epitaxial layer forms an under-gate floating antipole junction at the bottom part corresponding to the grid electrode; in a preferable example, the drain epitaxial layer forms a shield gate bottom floating antipolar column bottom junction at bottom portions corresponding to the source electrode extension inverted fins. According to the invention, a double-inverted-half-fin floating super-junction gate type field effect transistor framework is created for the first time, and the gain effect of uniformizing or helping uniformizing electron flows of the drain electrode on the back surface of the substrate and the source electrode on the top surface of the substrate is achieved.

An etching apparatus includes a chamber capable of being evacuated, a first electrode provided in the chamber and including a tray support portion configured to support a tray which can hold a plurality of substrates and load/unload the substrates into/from the chamber, and a voltage applying unit configured to apply a voltage to the first electrode. A dielectric plate is attached to a portion, of an obverse surface of the first electrode, which faces an outer edge portion of a non-target surface of the substrate.

A polarization-independent high-efficiency two-dimensional reflecting Dammann grating for wave band with central wavelength of 1064 nanometers is structurally characterized in that a fused quartz substrate is sequentially coated with an aluminum oxide film, a gold film, an aluminum oxide film and a fused quartz film, the aluminum oxide film between the gold film and the fused quartz film is a connection layer, and a rectangular-groove grating is etched on the fused quartz film layer. The grating cycle is 1,917-1,027 nanometers, the coordinate of a normalized phase mutation point is 0.265-0.275, the grating depth is 730-740 nanometers, and the connection layer is 92-102 nanometers thick. When TE (transverse electric) or TM (transverse magnetic) polarization light of the Dammann grating performs perpendicular incidence, 2*2 beam splitting of the wave band with the central wavelength of 1064 nanometers can be realized, the total diffraction efficiency is larger than 85% basically. The Dammann grating is machined with an optical hologram recording technique or by a laser direct writing device in combination with a microelectronic deep etching process and a film coating technique, materials are convenient to obtain, the manufacturing cost is low, large batch production can be realized, and the Dammann grating has important practical prospect.

The invention provides a manufacturing method of a super junction device, the super junction device, a chip and a circuit, and belongs to the technical field of semiconductors, and the manufacturing method comprises the steps: providing a substrate with an epitaxial layer; defining an etching region on the upper surface of the epitaxial layer; forming an etching groove with a first depth in the epitaxial layer by using an etching process according to the etching region; performing ion implantation on the bottom of the etching groove to form a doped region, wherein the doped region has a second conduction type, and the sum of the second depth and the first depth of the doped region is equal to the target depth; epitaxial filling is carried out on the etching groove to form a filling area, and a super junction is formed by a longitudinal doping area formed by the filling area and the doping area and an adjacent epitaxial layer area; a gate and a body region are formed, the body region is located at the top of the longitudinal doping region, and the gate is located on the upper surface of the epitaxial layer and covers part of the body region. Through the method provided by the invention, the uniformity of the etching depth of the groove is improved, the depth-to-width ratio of the groove is reduced, and epitaxial filling holes are improved.