Process method for truncating polysilicon gate of fin transistor

Abstract

The invention discloses a process method for truncating a polysilicon gate of a fin transistor. The process method comprises the following steps of step 1, forming fin bodies and a first groove between the fin bodies in a polysilicon gate formation region on a semiconductor substrate, and the fin bodies are not included in a polysilicon-free gate region and a second groove is formed; step 2, filling a first insulating layer; step 3, using a second photomask opposite to a first photomask that defines a polysilicon gate truncated region to define, and forming a first mask layer at the top of thefirst insulating layer in the second groove; step 4, etching back the first insulating layer, so as to define the height of the fin bodies; in the second groove, forming third grooves at the two sides of a coverage region of the first mask layer, and forming a polysilicon etching barrier layer by the first insulating layer between the third grooves; step 5, forming the polysilicon gate; and step6, after the polysilicon gate truncated region is opened by the first mask, performing polysilicon etching to achieve the truncation of the polysilicon gate. The process method for truncating the polysilicon gate of the fin transistor provided by the invention can increase process windows and improve the product yield.

Description

technical field [0001] The invention relates to the field of semiconductor integrated circuit manufacturing, in particular to a polysilicon gate cut-off process method for a fin transistor (FinFET transistor). Background technique [0002] In the existing Fin-type transistor logic chip process, the height of the polysilicon gate needs to be increased to meet the requirements of subsequent processes. The increase in the height of the polysilicon gate will cause insufficient window when the polysilicon gate is cut off in the process flow, which may cause short circuit problems in subsequent components. Such as Figure 1A to Figure 1B Shown is a schematic diagram of the device structure in each step of the polysilicon gate truncation process of the existing fin transistor; the polysilicon gate truncation process of the existing fin transistor includes the following steps: [0003] Step 1, such as Figure 1A As shown, a semiconductor substrate 101 is provided, and the semicondu...

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Problems solved by technology

[0014] Depend on Figure 1B It can be seen that the depth of polysilicon etching is relatively deep, and as the height of the polysilicon gate 106 increases, the depth of polysilicon etching will increase, which will make the polysilicon etching have a larger aspect ratio, Increased etching difficulty makes it easy to form polysilicon etching residues. For example, the polysilicon cannot be completely removed in the bottom area of ​​the groove formed by etching, that is, the area indicated by the dotted circle corresponding to the mark 108, which may cause short circuits in subsequent components. Reduce product yield

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