The invention provides a grid enhanced-power semiconductor field effect transistor which comprises a drain region (201), a drift region (202), a dielectric layer (203), a split grid (204), a grid electrode (205), an n+ layer (206), a source electrode (207) and a channel region (208), wherein K values of the dielectric layer (203) are distributed according to a certain law, namely, the K values become smaller from the source electrode to the drain electrode. In the grid enhanced-power semiconductor field effect transistor, the dielectric layer, the K values of which are distributed according to a certain law, is used for replacing an original side oxide structure, therefore, the drain-source on resistance is reduced on the condition that the withstand voltage of a device is not sacrificed. The transistor is compatible with the conventional MOSFET (metal-oxide-semiconductor field effect transistor) process, has very strong feasibility and can meet the application requirements of a power electronic system more easily.