The invention relates to a three-dimensional
system-level
chip normal installation stacking packaging structure formed by sealing first and then corroding and a technique method. The packaging structure comprises a
paddle (1) and pins (2).
Electricity conducting columns (3)are arranged on front faces of the pins (2). A
chip (4) is arranged on the front face of the
paddle (1) through
electricity-conducting or non-
electricity-conducting
adhesive substances. The front face of the
chip (4) is connected with front faces of the pins (2) through
metal wires (5).
Plastic packaging materials or
epoxy resin (7) wraps the area of the front face of the
paddle (1), areas of the front faces of the paddles (2) and the
peripheral area of the
electricity conducting columns(3), the
peripheral area of the chip (4), and the
peripheral area of the
metal wires (5). Anti oxidation
layers (8) are arranged on the surface, exposing out of the
plastic packaging materials or the
epoxy resin (7), of the paddle (1), the surfaces, exposing out of the
plastic packaging materials or the
epoxy resin (7), of the pins (2), and the surfaces, exposing out of the
plastic packaging materials or epoxy resin (7), of the electricity conducting columns (3). Packaging bodies (10) are stacked at tops of the electricity conducting columns (3) through electricity conducting substances (9). The packaging structure has the advantages of solving the problem that the quality of interconnected solder balls between packaging bodies is hard to control due to the fact that a lower layer
welding disk is lower than a lower layer plastic packaging face in traditional substate packaging stacking.