Packaging-after etching three-dimensional system-on-chip upright stacking packaging structure and technology method

Abstract

The invention relates to a packaging-after etching three-dimensional system-on-chip upright stacking packaging structure and a technology method. The packaging-after etching three-dimensional system-on-chip upright stacking packaging structure comprises a base island and pins, a chip is arranged in the front of the base island through conducting materials and non-conducting materials; the front of the chip is connected with the fronts of the pins through metal wires; conducting posts are arranged in the fronts of the pins; the region on the periphery of the base island, the region between the base island and the pins, the region between the pins, the region above the base island and the pins, the region below the base island and the pins, the chip, the metal wires and the conducting posts are all wrapped with molding compounds; packaging bodies are arranged on the tops of the conducting posts or the backs of the pins through conducting materials. The e packaging-after etching three-dimensional system-on-chip upright stacking packaging structure and the technology method have the advantages of solving the problem that because a bottom-layer substrate welding disc is lower than a bottom-layer plastic packing surface in a traditional substrate packaging stacking mode, the quality of interconnected welding balls between the packaging bodies is hard to control.

Description

Technical field [0001] The invention relates to a three-dimensional system-level chip front-mounting stacked packaging structure and a process method after etching and sealing. It belongs to the field of semiconductor packaging technology. Background technique [0002] The traditional and common PoP package stack structure is to stack the top storage device substrate package on the bottom logic device substrate package. The bottom device and the top device are mounted on solder balls and reflow soldering to achieve the stacking and electrical interconnection of the two packages. Such as Figure 81 . [0003] The aforementioned PoP (Package on Package) packaging structure has the following shortcomings: [0004] 1. The interconnecting pad between the bottom package and the top package is located on the substrate of the bottom package, lower than the plastic cover of the bottom package, so the molding height of the bottom package is limited by the size of the metal tin ball on the bot...

AI Technical Summary

Problems solved by technology

[0009] The purpose of the present invention is to overcome the above-mentioned shortcomings, and provide a three-dimensional system-in-package structure and process method for sealing first and then etching chips, which can solve the gap between packages caused by the traditional substrate package stacking due to the bottom substrate pad being lower than the bottom plastic cover. The problem that the quality of interconnection solder balls is difficult to control

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