637results about How to "Avoid etching" patented technology

A semiconductor transistor has a structure including a semiconductor substrate, a source region, a drain region and a channel region in between the source region and the drain region. A metal gate, having a top conductive portion of tungsten is provided above the channel region. A first silicon nitride protective layer over the source region and the drain region and a second silicon nitride protective layer over the gate region are provided. The first silicon nitride protective layer and the second silicon nitride protective layer are configured to allow punch-through of the first silicon nitride protective layer while preventing etching through the second silicon nitride protective layer. Source and drain silicide is protected by avoiding fully etching a gate opening unless either the etching used would not harm the silicide, or the silicide and source and drain contacts are created prior to fully etching an opening to the gate for a gate contact.

A single crystal M*N article, which may be made by a process including the steps of: providing a substrate of material having a crystalline surface which is epitaxially compatible with M*N; depositing a layer of single crystal M*N over the surface of the substrate; and removing the substrate from the layer of single crystal M*N, e.g., with an etching agent which is applied to the substrate to remove same, to yield the layer of single crystal M*N as said single crystal M*N article. The bulk single crystal M*N article is suitable for use as a substrate for the fabrication of microelectronic structures thereon, to produce microelectronic devices comprising bulk single crystal M*N substrates, or precursor structures thereof.

Micromachined, CMOS p+-active / n-well diodes are used as infrared sensing elements in uncooled Focal Plane Arrays (FPA). The FPAs are fabricated using a standard CMOS process followed by post-CMOS bulk-micromachining steps without any critical lithography or complicated deposition processes. Micromachining steps include Reactive Ion Etching (RIE) to reach the bulk silicon and anisotropic silicon wet etching together with electrochemical etch-stop technique to obtain thermally isolated p+-active / n-well diodes. The FPAs are monolithically integrated with their readout circuit since they are fabricated in any standard CMOS technology.

A semiconductor transistor has a structure including a semiconductor substrate, a source region, a drain region and a channel region in between the source region and the drain region. A metal gate, having a top conductive portion of tungsten is provided above the channel region. A first silicon nitride protective layer over the source region and the drain region and a second silicon nitride protective layer over the gate region are provided. The first silicon nitride protective layer and the second silicon nitride protective layer are configured to allow punch-through of the first silicon nitride protective layer while preventing etching through the second silicon nitride protective layer. Source and drain silicide is protected by avoiding fully etching a gate opening unless either the etching used would not harm the silicide, or the silicide and source and drain contacts are created prior to fully etching an opening to the gate for a gate contact.

The invention relates to a method for manufacturing microbridge of uncooled infrared focal plane detector and a structure thereof.The method comprises the following steps: preparing a reflecting layer on a readout circuit-based wafer;an insulated medium layer,a first sacrificial layer and a first supporting layer;etching the first supporting layer and preparing a first through hole above the reflecting layer;preparing a fist electrode,a first medium layer,a first passivation layer, a second sacrificial layer,a second supporting layer,a thermal layer and a protective layer;etching the second supporting layer and preparing a second through hole above the first electrode;etching the protective layer and preparing a contact hole above the thermal layer;preparing a second electrode, a second medium layer, a second passivation layer,a third sacrificial layer,a third supporting layer and a third passivation layer successively;releasing respective sacrificial layers to get the detector structure.With the three-layer microbridge structure,the method for manufacturing microbridge of uncooled infrared focal plane detector increases effective filling factors and makes infrared absorption more efficient.

A method for fabricating a semiconductor device is disclosed. The method includes providing a substrate; forming at least one gate structure over the substrate; forming a plurality of doped regions in the substrate; forming an etch stop layer over the substrate; removing a first portion of the etch stop layer, wherein a second portion of the etch stop layer remains over the plurality of doped regions; forming a hard mask layer over the substrate; removing a first portion of the hard mask layer, wherein a second portion of the hard mask layer remains over the at least one gate structure; and forming a first contact through the second portion of the hard mask layer to the at least one gate structure, and a second contact through the second portion of the etch stop layer to the plurality of doped regions.

A method of forming a GAA MOSFET includes providing a substrate having source, drain and channel regions, the substrate doped with one of a p-type and an n-type dopant. Disposing an etch stop-electric well (ESEW) layer over the substrate, the ESEW layer doped with the other of the p-type and the n-type dopant. Disposing a sacrificial layer over the ESEW layer, the sacrificial layer doped with the same type dopant as the substrate. Disposing a channel layer over the sacrificial layer. Patterning a fin out of the ESEW layer, sacrificial layer and channel layer in the channel region. Selectively etching away only the sacrificial layer of the fin to form a nanowire from the channel layer of the fin while the ESEW layer of the fin functions as an etch stop barrier to prevent etching of trenches in the substrate.

A single crystal M*N article, which may be made by a process including the steps of: providing a substrate of material having a crystalline surface which is epitaxially compatible with M*N; depositing a layer of single crystal M*N over the surface of the substrate; and removing the substrate from the layer of single crystal M*N, e.g., with an etching agent which is applied to the substrate to remove same, to yield the layer of single crystal M*N as said single crystal M*N article. The bulk single crystal M*N article is suitable for use as a substrate for the fabrication of microelectronic structures thereon, to produce microelectronic devices comprising bulk single crystal M*N substrates, or precursor structures thereof.

A semiconductor substrate is patterned to form a depression and prominence. A floating gate is formed so as to cover at least both sidewalls of the prominence of the depression and prominence, and is then etched to form a trench for a device isolation self-aligned with the floating gate. Related structures are also described.

Various processes and related systems are provided for making structures on substrate surfaces. Disclosed are methods of making a structure supported by a substrate by providing a substrate having a receiving surface and exposing at least a portion of the receiving surface to output from a remote plasma of an inert gas. The remote plasma has an energy low enough to substantially avoid etching or sputtering of the receiving surface but sufficient to generate a treated receiving surface. The treated surface is contacted with a deposition gas, thereby making the structure supported by the substrate.

A micromechanical component is described including a substrate having a spacer layer and a test structure for ascertaining the thickness of the spacer layer. The test structure includes a seismic mass, which is elastically deflectable along a measuring axis parallel to the substrate, a first electrode system and a second electrode system for deflecting the seismic mass along the measuring axis, having a mass electrode, which is produced by a part of the seismic mass, and a substrate electrode, which is situated on the substrate in each case, the first electrode system being designed to be thicker than the second electrode system by the layer thickness of the spacer layer.

In a method for manufacturing a micromechanical semiconductor component, e.g., a pressure sensor, a locally limited, buried, and at least partially oxidized porous layer is produced in a semiconductor substrate. A cavity is subsequently produced in the semiconductor substrate from the back, directly underneath the porous first layer, using a trench etch process. The porous first layer is used as a stop layer for the trench. Thin diaphragms having a low thickness tolerance may thus be produced for differential pressure measurement.

The invention provides a manufacturing method of separated gate type flash memories embedded into logic circuits. Compared with a method of separately manufacturing the separated gate type flash memories, the manufacturing method includes four additional steps of once more polycrystalline deposition, once more silicon oxide deposition, once more etching and once more fluid coverage. The characteristic of good fluidity of fluid materials is utilized, grooves, especially deep grooves can be filled, and areas required to be protected can be prevented from being etched in the etching step. The separated gate type flash memories manufactured by the method are embedded into peripheral circuits of high-voltage transistors and logic transistors so that the separated gate type flash memories, the high-voltage transistors and the logic transistors can be manufactured on one integrated circuit, and the integration of the separated gate type flash memories, the high-voltage transistors and the logic transistors is high in density and quick in running. Further, integrated chips are smaller so that cost of each integrated chip is lowered.

Techniques herein include methods of patterning substrates such as for back end of line (BEOL) metallization processes. Techniques herein enable fully self-aligned vias and lines. Processes herein include using selective deposition, protective films and combination etch masks for accurately patterning a substrate. In a substrate having uncovered portions of metal material and dielectric material, the dielectric material is grown upwardly without covering metal material. This raised dielectric material is conformally protected and used in subsequent patterning step to align via and line placement. Such combinations mitigate overlay errors.