1026 results about "Electronic structure" patented technology

Disclosed is a method of fabricating a molded structure including both micro lenses and metallic pins. The method comprises the steps of providing a mold apparatus having a set of first cavities and a set of second cavities, depositing a first material in the first cavities to form a set of metallic pins, and depositing a second material in the second cavities to form a set of micro lenses. The formed molded structure comprises a substrate, a set of molded microlenses on said substrate, and a set of molded metallic pins on that same substrate. The metallic pins may be formed as alignment pins or as electrical connectors. The invention enables the micro lenses and metallic pins to be manufactured by way of molding on a common substrate for the first time.

A tiled display device is formed from display tiles having picture element (pixel) positions defined up to the edge of the tiles. Each pixel position has an organic light-emitting diode (OLED) active area which occupies approximately 25 percent of the pixel area. Each tile includes a memory which stores display data, and pixel driving circuitry which controls the scanning and illumination of the pixels on the tile. The pixel driving circuitry is located on the back side of the tile and connections to pixel electrodes on the front side of the tile are made by vias which pass through portions of selected ones of the pixel areas which are not occupied by the active pixel material. The tiles are to formed in two parts, an electronics section and a display section. Each of these parts includes connecting pads which cover several pixel positions. Each connecting pad makes an electrical connection to only one row electrode or column electrode. The connecting pads on the display section are electrically connected and physically joined to corresponding connecting pads on the electronics section to form a complete tile. Each tile has a glass substrate on the front of the tile. Black matrix lines are formed on the front of the glass substrate and the tiles are joined by mullions which have the same appearance as the black-matrix lines. Alternatively, the black matrix lines may be formed on the inside surface of an optical integrating plate and the tiles may be affixed to the integrating plate such that the edges of the joined tiles are covered by the black-matrix lines. A cathodoluminescent tile structure is formed from individual tiles that have multiple phosphor areas, a single emissive cathode and horizontal and vertical electrostatic deflecting grids which deflect the electron beam produced by the single cathode onto multiple ones of the phosphor areas.

The present invention provides novel methods of fabricating microelectronics structures, and the resulting structures formed thereby, using EUV lithographic processes. The method involves utilizing an assist layer immediately below the photoresist layer. The assist layer can either be directly applied to the substrate, or it can be applied to any intermediate layer(s) that may be applied to the substrate. The preferred assist layers are formed from spin-coatable, polymeric compositions. The inventive method allows reduced critical dimensions to be achieved with improved dose-to-size ratios, while improving adhesion and reducing or eliminating pattern collapse issues.

A single crystal M*N article, which may be made by a process including the steps of: providing a substrate of material having a crystalline surface which is epitaxially compatible with M*N; depositing a layer of single crystal M*N over the surface of the substrate; and removing the substrate from the layer of single crystal M*N, e.g., with an etching agent which is applied to the substrate to remove same, to yield the layer of single crystal M*N as said single crystal M*N article. The bulk single crystal M*N article is suitable for use as a substrate for the fabrication of microelectronic structures thereon, to produce microelectronic devices comprising bulk single crystal M*N substrates, or precursor structures thereof.

The present invention relates to systems, materials and methods for the formation of conducting, semiconducting, and dielectric layers, structures and devices from suspensions of nanoparticles. Drop-on-demand systems are used in some embodiments to fabricate various electronic structures including conductors, capacitors, FETs. Selective laser ablation is used in some embodiments to pattern more precisely the circuit elements and to form small channel devices.

Dielectric materials including elements of Si, C, O and H having specific values of mechanical properties (tensile stress, elastic modulus, hardness cohesive strength, crack velocity in water) that result in a stable ultra low k film which is not degraded by water vapor or integration processing are provided. The dielectric materials have a dielectric constant of about 2.8 or less, a tensile stress of less than 45 MPa, an elastic modulus from about 2 to about 15 GPa, and a hardness from about 0.2 to about 2 GPa. Electronic structures including the dielectric materials of the present invention as well as various methods of fabricating the dielectric materials are also provided.

A gap conductor structure for an integrated electronic circuit that may function as an electronic fuse device or as a low capacitance inter level signal line is integrated as part of the semi-conductor chip wiring. The gap conducting structure includes one or more air gap regions of predefined volume that fully or partially exposes a length of interlevel conductor layer in an IC. Alternately, the air gap region may wholly located within the dielectric region below a corresponding conductor and separated by insulator. When functioning as a fuse, the gap region acts to reduce thermal conductivity away from the exposed portion of the conductor enabling generation of higher heat currents in the conducting line with lower applied voltages sufficient to melt a part of the conducting line. The presence of gaps, and hence, the fuses, are scalable and may be tailored to the capacity of currents they must carry with the characteristics of the fuses defined by a circuit designer. Furthermore, conducting structures completely or partially exposed in the air gap may function as low capacitance minimum delay transmission lines.< / PTEXT>

Methods in accordance with aspects of this invention form microelectronic structures in accordance with other aspects of this invention, such as non-volatile memories, that include (1) a layerstack having a pattern including sidewalls, the layerstack comprising a resistivity-switchable layer disposed above and in contact with a bottom electrode, and a top electrode disposed above and in contact with the resistivity-switchable layer; and (2) a dielectric sidewall liner in contact with the sidewalls of the layerstack; wherein the resistivity-switchable layer includes a carbon-based material, and the dielectric sidewall liner includes an oxygen-poor dielectric material. Numerous additional aspects are provided.

An out of the box signage kit facilitates in field conversion of a static billboard having an anchored planar mounting structure into a large format billboard type electronic sign that includes a plurality of interchangeable weatherized display modules; a plurality of hand mountable interchangeable structural frames for supporting the plurality of weatherized display modules, each structural frame having a back portion for mounting to a frontside of the anchored planar mounting structure and a front portion defining a plurality of bay members for receiving corresponding ones of said plurality of weatherized display modules; and a plurality of interchangeable wire harnesses, each individual wire harness including a first end for coupling to a power source mounted on a backside of the anchored planar mounting structure, each individual wire harness having a plurality of power extensions for coupling the power source to at least one of the display modules.

Apparatuses and methods for forming microelectronic assemblies are claimed. One embodiment of the invention includes a contact smart card wherein fluidic self assembly is used to build the microelectronic structures on the microelectronic assembly such that a contact smart data is transmitted unidirectionally. A contact smart card is inserted directly into a device that transfers data to a microelectronic assembly coupled to the smart card. Another embodiment of the invention relates to a contactless smart card in which fluidic self assembly is also used here to build the microelectronic assembly. Data is transmitted to an antenna that is embedded in the contactless card in which a plurality of blocks were deposited thereon.

Reconfigurable electronic structures and circuits using programmable, non-volatile memory elements. The programmable, non-volatile memory elements may perform the functions of storage and / or a switch to produce components such as crossbars, multiplexers, look-up tables (LUTs) and other logic circuits used in programmable logic structures (e.g., (FPGAs)). The programmable, non-volatile memory elements comprise one or more structures based on Phase Change Memory, Programmable Metallization, Carbon Nano-Electromechanical (CNT-NEM), or Metal Nano-Electromechanical device technologies.

A method for fabricating a SiCOH dielectric material comprising Si, C, O and H atoms from a single organosilicon precursor with a built-in organic porogen is provided. The single organosilicon precursor with a built-in organic porogen is selected from silane (SiH4) derivatives having the molecular formula SiRR1R2R3, disiloxane derivatives having the molecular formula R4R5R6—Si—O—Si—R7R8R9, and trisiloxane derivatives having the molecular formula R10R11R12—Si—O—Si—R13R14—O—Si—R15R16R17 where R and R1-17 may or may not be identical and are selected from H, alkyl, alkoxy, epoxy, phenyl, vinyl, allyl, alkenyl or alkynyl groups that may be linear, branched, cyclic, polycyclic and may be functionalized with oxygen, nitrogen or fluorine containing substituents. In addition to the method, the present application also provides SiCOH dielectrics made from the inventive method as well as electronic structures that contain the same.

The invention relates to a process for producing an electronic structure that includes a thin layer of strained semiconductor material from a donor wafer. The donor wafer has a lattice parameter matching layer that includes an upper layer of a semiconductor material having a first lattice parameter and a film of semiconductor material having a second, nominal, lattice parameter that is substantially different from the first lattice parameter and that is strained by the matching layer. This process includes transfer of the film to a receiving substrate. The invention also relates to the semiconductor structures that can be produced by the process.