134 results about "In situ etching" patented technology

In accordance with the present invention, improved methods for reducing the dislocation density of nitride epitaxial films are provided. Specifically, an in-situ etch treatment is provided to preferentially etch the dislocations of the nitride epitaxial layer to prevent threading of the dislocations through the nitride epitaxial layer. Subsequent to etching of the dislocations, an epitaxial layer overgrowth is performed. In certain embodiments, the etching of the dislocations occurs simultaneously with growth of the epitaxial layer. In other embodiments, a dielectric mask is deposited within the etch pits formed at the dislocations prior to the epitaxial layer overgrowth.

A process is provided for depositing an undoped silicon oxide film on a substrate disposed in a process chamber. A process gas that includes SiF₄, H₂, a silicon source, and an oxidizing gas reactant is flowed into the process chamber. A plasma having an ion density of at least 10¹¹ ions/cm³ is formed from the process gas. The undoped silicon oxide film is deposited over the substrate with the plasma using a process that has simultaneous deposition and sputtering components. A temperature of the substrate during such depositing is greater than 450° C.

Thermal control is provided for an extraction electrode of an ion-beam producing system that prevents formation of deposits and unstable operation and enables use with ions produced from condensable vapors and with ion sources capable of cold and hot operation. Electrical heating of the extraction electrode is employed for extracting decaborane or octadecaborane ions. Active cooling during use with a hot ion source prevents electrode destruction, permitting the extraction electrode to be of heat-conductive and fluorine-resistant aluminum composition. The service lifetime of the system is enhanced by provisions for in-situ etch cleaning of the ion source and extraction electrode, using reactive halogen gases, and by having features that extend the service duration between cleanings, including accurate vapor flow control and accurate focusing of the ion beam optics. A remote plasma source delivers F or Cl ions to the de-energized ion source for the purpose of cleaning deposits in the ion source and the extraction electrode. These techniques enable long equipment uptime when running condensable feed gases such as sublimated vapors, and are particularly applicable for use with so-called cold ion sources and universal ion sources. Methods and apparatus are described which enable long equipment uptime when decaborane and octadecaborane are used as feed materials, as well as when vaporized elemental arsenic and phosphorus are used, and which serve to enhance beam stability during ion implantation.

The service lifetime of an ion source is enhanced or prolonged by the source having provisions for in-situ etch cleaning of the ion source and of an extraction electrode, using reactive halogen gases (F or Cl), and by having features that extend the service duration between cleanings. The latter include accurate vapor flow control, accurate focusing of the ion beam optics, and thermal control of the extraction electrode that prevents formation of deposits or prevents electrode destruction. An apparatus comprised of an ion source for generating dopant ions for semiconductor wafer processing is coupled to a remote plasma source which delivers F or Cl ions to the first ion source for the purpose of cleaning deposits in the first ion source and the extraction electrode. These methods and apparatus enable long equipment uptime when running condensable feed gases such as sublimated vapor sources, and are particularly applicable for use with so-called cold ion sources. Methods and apparatus are described which enable long equipment uptime when decaborane and octadecarborane are used as feed materials, as well as when vaporized elemental arsenic and phosphorus are used, and which serve to enhance beam stability during ion implantation.

By patterning a spacer layer stack and etching a cavity in an in situ etch process, the process complexity, as well as the uniformity, during the formation of embedded strained semiconductor layers may be significantly enhanced. In an initial phase, the spacer layer stack may be patterned on the basis of an anisotropic etch step with a high degree of uniformity, since a selectivity between individual stack layers may not be necessary. Thereafter, a cleaning process may be performed followed by a cavity etch process, wherein a reduced over-etch time during the spacer patterning process significantly contributes to the uniformity of the finally obtained cavities, while the in situ nature of the process also provides a reduced overall process time.

This invention adds to the art of replacement source-drain cMOS transistors. Processes may involve etching a recess in the substrate material using one equipment set, then performing deposition in another. Disclosed is a method to perform the etch and subsequent deposition in the same reactor without atmospheric exposure. In-situ etching of the source-drain recess for replacement source-drain applications provides several advantages over state of the art ex-situ etching. Transistor drive current is improved by: (1) Eliminating contamination of the silicon-epilayer interface when the as-etched surface is exposed to atmosphere and (2) Precise control over the shape of the etch recess. Deposition may be done by a variety of techniques including selective and non-selective methods. In the case of blanket deposition, a measure to avoid amorphous deposition in performance critical regions is also presented.

When forming sophisticated gate electrode structures requiring a threshold adjusting semiconductor alloy for one type of transistor, a recess is formed in the corresponding active region, thereby providing superior process uniformity during the deposition of the semiconductor material. Due to the recess, any exposed sidewall surface areas of the active region may be avoided during the selective epitaxial growth process, thereby significantly contributing to enhanced threshold stability of the resulting transistor including the high-k metal gate stack.

The invention discloses a gallium nitride homoepitaxy method based on in situ etching. The method comprises the following steps: 1) selecting a gallium nitride substrate and transferring the substrate into an MOCVD system; 2) conducting fast etching on the substrate for a short time; 3) conducting long-time slow etching after the fast etching to form hexagonal pyramid micro structures on the substrate surface; 4) laterally growing to merge the hexagonal pyramid micro structures; and 5) continuing to grow a high-quality GaN epitaxial layer on the merged film. The invention has the following advantages: through the control of components of in situ etching gas, impurities on the surface of the substrate are removed, while the hexagonal pyramid micro structures are formed on the surface of the substrate; and the micro structures are merged in a lateral epitaxial stage, so as to reduce the dislocation density of the epitaxial layer and finally obtain the gallium nitride epitaxial thin film with high quality. Formation of hexagonal pyramid micro structures on the surface of the substrate does not need additional process equipment; the method is economical, simple and practicable; and the epitaxial material has good performance. Therefore, the method provided by the invention is an effective solution for realizing high-quality and low-cost growth of GaN epitaxial thin film.

A method for fabricating a semiconductor device, wherein the method comprises steps as follows: a semiconductor structure comprising a substrate, a dummy gate structure having a dielectric layer disposed over the substrate and a silicon layer disposed over the dielectric layer, and an etching stop layer (ESL) and an inter-layer dielectric (ILD) layer both of which are sequentially disposed over the substrate and the dummy gate structure is first provided. Then, a chemical mechanical polishing (CMP) is performed to planrizing the ILD layer and expose the ESL. Subsequently, an in-situ etching process is conducted to remove portions of the ESL and the silicon layer to form an opening in the dummy gate structure. Next, metal material is filled into the opening.

The invention discloses a P-type heavily-doped silicon carbide film extension preparation method, which mainly solves the problem that in the prior art, high-quality heavy doping of silicon carbide cannot be realized. The method comprises the following steps that: a silicon carbide underlay is firstly placed into a reaction chamber; the reaction chamber is heated in the hydrogen stream, and after the temperature reaches 1,400 DEG C, propane (C3H8) is added into the hydrogen stream; after the temperature reaches 1,580 DEG C, in-situ etching is performed on the underlay for 10 to 30 minutes; then the temperature of the reaction chamber is maintained at 1,580 DEG C, the air pressure is maintained at 100mbar, silane (SiH4) with a flow rate of 15 to 24 mL/min, C3H8 with a flow rate of 5 to 10 mL/min and trimethyl aluminium with a flow rate of 3.2*10<minus 5 mol/min) are added into the hydrogen stream of 20L/min to grow an extension layer; after the growth is completed, the extension layer is cooled in the hydrogen stream; and finally, argon is charged into the reaction chamber to the normal pressure. The doping concentration of the prepared silicon carbide extension layer is 4*1019cm<-3> to 4.6*1019cm<-3>, the doping is uniform, the surface is smooth, and the prepared silicon carbide extension layer can be used for producing a silicon carbide device.

A method for preparing nanocrystals is disclosed. The method includes synthesizing colloidal semiconductor nanocrystal cores, and adding a metal salt to the colloidal semiconductor nanocrystal cores and heating the mixture while maintaining the reaction temperature constant. During the reaction, the surfaces of the semiconductor nanocrystal cores are etched (‘in-situ etching’) and metal-surfactant layers are formed on the etched surface portions of the semiconductor nanocrystal cores. The metal-surfactant layers are derived from the metal salt. Nanocrystals prepared by the method have minimal surface defects and exhibit high luminescence efficiency and good stability.

The present invention discloses a novel composite substrate which solves the problem associated with the quality of substrate surface. The composite substrate has at least two layers comprising the first layer composed of Ga_xAl_yIn_1-x-yN (0≦x≦1, 0≦x+y≦1) and the second layer composed of metal oxide wherein the second layer can be removed with in-situ etching at elevated temperature. The metal oxide layer is designed to act as a protective layer of the first layer until the fabrication of devices. The metal oxide layer is designed so that it can be removed in a fabrication reactor of the devices through gas-phase etching by reactive gas such as ammonia.