80results about How to "Simplify process complexity" patented technology

The invention discloses a high temperature superconductor coil and a winding technology of the high temperature superconductor coil. The high temperature superconductor coil comprises an epoxy barrel and a plurality of layers of coil units, wherein each coil unit is composed of a low temperature glue layer, a polyimide film layer and a superconduction strip layer which are arranged in sequence. According to the winding technology, firstly, a framework of the superconductor coil is well fixed, winding positions are marked, the surface of the framework is evenly coated with low temperature glue and wound with polyimide films, then polyimide belts are laid at equal intervals, tensioned and fixed, after a strip winding disc is prepared, the wire inlet end is fixed to the surface of the framework and is evenly and densely wound with a layer of superconduction strips, then the surface of each strip is coated with the low temperature glue and wound with a layer of polyimide films, the polyimide belts are tensioned and laid backwards, and all the operations are repeated until the whole coil is wound. It is guaranteed that certain prestress is applied to the superconduction strips, layer insulation is achieved through the polyimide films and the low temperature glue, and the winding technology is simple and effective on the basis of ensuring the performance of the strips effectively.

An edge enhancement method and apparatus for Bayer images are provided. The apparatus stores the raw Bayer image data into a line buffer. After having directly read the raw Bayer image data from the buffer, the apparatus computes luminance characteristic values, analyzes the edge characteristic and then outputs the edge characteristic values. According to the edge characteristic values, the edges in the raw Bayer image data are enhanced. The apparatus simplifies the processing complexity of the rear-stage circuit by directly enhancing the edges in the Bayer image, and is easily combined with the post image processing mechanism. Conventionally, the raw Bayer image is converted to the RGB image or the YUV image and then the edge enhancement operation is performed. The invention reduces the computing volume and memory size. Also, performing the edge enhancement operation in advance helps to identify the interpolation direction and ease the annoying noise.

The invention provides an EVA (ethylene-vinyl acetate) precoating packaging adhesive film and a preparation method thereof. The adhesive film is composed of three layers, wherein the middle layer is a BOPP (biaxially-oriented polypropylene) film layer, and the upper and lower layers are respectively an EVA adhesive layer. The EVA adhesive layer is prepared from 100 parts of ethylene-vinyl acetate copolymer, 0.5-1 part of crosslinking agent, 0.1-2 parts of antioxidant, 0.01-0.02 part of light stabilizer and 0.02-0.04 part of tackifier. A precoating technique is adopted to produce the EVA packaging adhesive film, i.e. the EVA adhesive layers are coated to the upper and lower surfaces of the BOPP film layer to constitute the EVA packaging adhesive film, thereby greatly enhancing the production rate and simplifying the technique complexity degree under the support of the BOPP film. The bonding firmness between the EVA adhesive layer and BOPP film layer is enhanced, and the shock strength and environmental stress crack resistance of the adhesive film are enhanced.

A 3-D Single Floating Gate Non-Volatile Memory (SFGNVM) device based on the 3-D fin Metal-Oxide-Semiconductor Field Effect Transistor (MOSFET) is disclosed. The disclosed Non-Volatile Memory (NVM) device consists of a pair of semiconductor fins and one floating metal gate. The floating metal gate for storing electrical charges to alter the threshold voltage of the fin MOSFET crosses over the pair of semiconductor fins on top of coupling and tunneling dielectrics above the surfaces of the two semiconductor fins. One semiconductor fin with the same type impurity forms the control gate of the non-volatile memory device. The other semiconductor fin is doped with opposite type of impurity in the channel regions under the metal floating gate and with the same type of impurity in the source and drain regions on the sides of the crossed metal floating gate.

A method for manufacturing a bonded wafer with ultra-thin single crystal ferroelectric film is provided, comprising the following steps: providing a single crystal ferroelectric wafer and a carrier wafer while activating the surfaces of the single crystal ferroelectric wafer and the carrier wafer; bonding the activated surface of the single crystal ferroelectric wafer to the activated surface of the carrier wafer; and thinning the single crystal ferroelectric wafer for forming an ultra-thin single crystal ferroelectric film. Wherein, the thinning process in the aforesaid preferred embodiment is the method of polishing, grinding, chemical mechanical polishing, or etching. And the bonding force generated in the bonding process is strong enough to resist the shearing force.