73results about How to "Improve safe work area" patented technology

This invention describes implementation of medium / high voltage semiconductor devices with a better voltage-blocking capability versus specific on-resistance trade off. This approach can be implemented in baseline and submicron CMOS without any additional process steps. CMOS semiconductor devices, such as transistors, are known. Typically these 5 devices have only limited applicability in high voltage (HV) due to for instance breakdown of voltage. Many IC (Integrated Circuit) applications require for instance power management units for DC:DC down-or up-conversion of the supply voltage. Typically NMOS and PMOS semiconductor devices, such as transistors, with capability from10 V up 10 to 25 V are required for such applications.

The invention provides a semiconductor transverse device and a high-voltage device. The semiconductor transverse device is provided with three external connection terminals, utilizes two current carriers to conduct electricity and comprises a highest voltage area and a lowest voltage area which both take a substrate as zero-voltage, and a surface voltage resisting area is formed between the highest voltage area and the lowest voltage area. The highest voltage area and the lowest voltage area are internally provided with an external connection terminal and a control terminal respectively, wherein one control terminal is in external connection and controls one type of current carrier flow, and the other control terminal is built in and controls the other type of current carrier flow; and an electric potential on the built-in control terminal is adjusted and controlled by the external voltage of external-connection control terminal. The attached drawing in the abstract shows a method for manufacturing the devices by using an n-MOSFET to control electron current and a pnp bipolar transistor to control cavity current, wherein the electric potential of the base region of the pnp bipolar transistor is adjusted and controlled by external voltage on an n-MOSFET gate electrode.

Provided is a crosswise heterogeneous electron irradiation method of improving a global completion table (GCT) chip safe working area. The crosswise heterogeneous electron irradiation method of improving the GCT chip safe working area comprises the following steps: (1) carrying out pre-radiation of a GCT chip, and carrying out a primary pre-irradiation to the GCT chip through methods of controlling minority carrier lifetime and pressure drop of the GCT chip, (2) carrying out monitoring of the minority carrier lifetime and pressure drop of the GCT chip after a primary annealing, (3) adopting composite alloy baffles, carrying out a second irradiation and a second annealing to the GCT chip by using heterogeneity of electron irradiation penetrating through the composite alloy baffles, and (4) carrying out the monitoring of the minority carrier lifetime and pressure drop of the GCT chip again. The crosswise heterogeneous electron irradiation method of improving the GCT chip safe working area has the advantages of being simple in principle, and simple and convenient to operate, achieving control of the minority carrier lifetime of parts of the GCT chip, reducing redistribution effect of an electric current in the process of cutoff of GCT by reducing the minority carrier lifetime of far from gate pole slivers, and improving a whole safe working area of the GCT chip and the like.