High voltage MOS device

Abstract

The invention provides a high-voltage MOS device, which at least includes a grid, a source and a drift region, wherein, the device further includes at least two field plates which are mutually separated with certain distance and are distributed at the upper surface of the drift region, the field plate which is nearest to the grid is connected with the source, and the other field plate is connected with the grid. The two field plates are both composed of polysilicon layers, and the thickness is the same as the thickness of the polysilicon layers. The lengths of the two filed plates can be same or different. The length of the field plate is decided by the doping level of the drift area, the lower the doping level of the drift area is, the longer the filed plate is, and the length of the filed plate is not more than one third of the length of the drift region. The length of the field plate is more than one sixth and less than one fourth of the length of the drift region. Compared with the prior art, the device of the invention can improve breakdown voltage and reduce on-resistance, the speed of the device is not affected and safe working area is larger.

Description

technical field [0001] The invention relates to a high-voltage MOS device, in particular to a high-voltage MOS device. Background technique [0002] The application of high-voltage MOS devices is more and more extensive. Evaluating the performance of high-voltage devices generally includes three indicators: breakdown voltage, on-resistance, and switching speed; evaluating the reliability of high-voltage devices generally includes two indicators: safe operating area and performance degradation caused by hot electron injection. [0003] LDMOS (Laterally Diffused Metal Oxide Semiconductor) is the core device of SOI high-voltage intelligent power integrated circuits, and has become a hot spot in the research of semiconductor power devices in recent years. The withstand voltage of the LDMOS structure depends on the smaller of the lateral withstand voltage and the vertical withstand voltage of the device. The lateral withstand voltage of the device can be improved by using the s...

AI Technical Summary

Problems solved by technology

Among them, Figure 1(a) is an ordinary LDMOS, and Figure 1(b) is an LDMOS using gate polysilicon 13 as a field plate. This structure improves the breakdown voltage and reduces the on-resistance. The disadvantage is that the speed is not fast, and it works safely. small area

[0005] Figure 1(c) is a MOS device in which the field plate 17 and the source 11 are connected together. This structure also increases the breakdown voltage, and the speed is not affected. The disadvantage is that the on-resistance is increased

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