Novel plastic packaging structure for power MOS

Abstract

The invention relates to a novel plastic packaging structure for a power MOS. The novel plastic packaging structure comprises a frame, a chip, and a packaging body. The frame is a copper frame having two parts; one part of the copper frame is used as a piece of slide glass and is connected with a back electrode of a device and a pin is led out to form electrical connection; and the other part of the copper frame is a cooling back panel for realizing a heat radiation function; and the two parts are isolated from each other by a high-thermal-conduction isolation layer, so that the two parts of the copper frame are in physical connection. According to the invention, because the slide glass and the cooling panel are independent parts isolated from each other and the slide glass is used for electrical connection and the cooling panel is used for providing a cooling channel, PCB assembling becomes convenient and the packaging thermal resistance of the power MOS can be reduced, and the security working zone at an application terminal is enhanced; and advantages of high power and low power consumption of the power MOS are fully realized.

Description

technical field [0001] The invention relates to a novel plastic encapsulation structure suitable for power MOS. Background technique [0002] As one of the main branches of power semiconductor devices, power field effect transistors (POWER MOS) are widely used in power supplies or adapters for consumer electronics such as mobile phones, computers, lighting and LCD TVs. Power MOS devices also have input impedance bottoms, Fast switching speed and other advantages. With the development of semiconductor technology, power MOS devices with high power, low power consumption and small package are attracting more and more people's attention. [0003] Power MOS devices are generally composed of many transistors with a cell structure connected in parallel. The structure and manufacturing process of the chip are the decisive factors for its performance quality, and further improvement of these technologies will pay a high cost. The package is a channel for communicating between the s...

AI Technical Summary

Problems solved by technology

Generally, in order to simplify the process and better heat dissipation conditions, the chip 4' is pasted on the frame 1' by solder, and the back electrode (such as the drain of the power MOS) is directly connected to the back plate of the frame. The back electrode can pass through the middle The pins can also be connected to the external circuit through the backplane. The frame material is made of Cu with excellent thermal conductivity and electrical performance. If it is an in-line package, the backplane of the frame 1' needs to be soldered to the PCB board Add a heat sink, and the half-encapsulated package has an exposed backplane. In order to prevent short circuits, an insulating pad needs to be installed between the backplane and the heat sink. This will add a step to the process and affect the quality of the product. Production efficiency; in order to prevent this situation, when molding, the backplane of the frame can be completely wrapped with plastic molding compound to form a fully encapsulated package (Fullpak), which can avoid the use of insulating pads, but fully encapsulated devices Due to the poor thermal conductivity of the plastic encapsulation compound itself, the thermal resistance of the fully encapsulated device is doubled, which greatly affects the performance of the device. For power MOS, it also has a certain impact on the reliability of its UIS.

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