38 results about "Hot holes" patented technology

A non-volatile memory low voltage and high speed erasure method, the non-volatile memory is realized through disposing a stacked gate structure having a control gate and a floating gate on a semiconductor substrate or in an isolation well, such that adequate hot holes are generated in proceeding with low voltage and high speed erasure operation through a drain reverse bias and making changes to gate voltage. In addition, through applying positive and negative voltages on a drain, a gate, and a semiconductor substrate or well regions, adequate hot holes are generated, so as to lower the absolute voltage in achieving the objective of reducing voltage of erasing memory.

A method for performing an erase operation is disclosed in a non-volatile memory having a plurality of memory cells. At least one memory cell is programmed having a threshold voltage level in a first region before programming, and after programming the memory cell has a threshold voltage level in a second region, wherein the second region is higher in threshold voltage than the fist region. The erasing operation implements a programming of memory bits that can inject negative charge carriers or electrons into a memory cell instead of using the conventional technique of injecting hot holes into the memory cell. This can avoid room temperature drift and charge loss caused by hot hole injection.

Methods for removing, or leaching, cobalt or other diamond-diamond bonding catalysts from polycrystalline diamond compacts (PDCs) or other structures formed from polycrystalline diamond include leaching under conditions that simulate use of PDCs in a hot hole drilling environment. A leaching agent may be formulated, when used under appropriate conditions, to remove or substantially remove cobalt or another catalyst from polycrystalline diamond without dissolving, degrading or otherwise attacking a substrate that supports or carries the polycrystalline diamond. The leaching agent may include one or more components that mimick the chemicals or conditions to which a PDC would be exposed in a hot hole drilling environment. Polycrystalline diamond structures from which cobalt or another diamond-diamond bonding catalyst has been removed or substantially removed are also disclosed, as are systems for leaching cobalt or other diamond-diamond bonding catalysts from polycrystalline diamond.

The invention provides a flash memory unit, a flash memory array and an operation method thereof, comprising: an N well is formed in a P-type substrate, a P-type doped region is formed in the N well, and the P-type doped region is used as the first A source, a second source, and a drain; the gate structure on the N well is located between the first source and the second source, and the gate structure has a symmetrical shape about the erasing gate Two storage bits, each containing a floating gate and a word line gate. The flash memory unit provided by the present invention is programmed by generating high-energy electrons or even hot electrons through the collision ionization of hot holes at the drain pinch-off point, which is beneficial to the miniaturization of the device and achieves the purpose of reducing the area of ​​the device unit, and the flash memory unit provided by the present invention With a special erasing gate, it can be erased without applying high voltage to the word line gate, so that the second oxide layer under the word line gate can be made very thin, so the read voltage can be very small, which simplifies the design of the read circuit .

The invention belongs to a integrated circuit reliability test technology field and especially relates to a multifunctional test circuit of integrated circuit stress degradation and a test method thereof. A core part of the test circuit takes an annular oscillator as a basis. Several auxiliary transistors, switch transistors and control terminals are added. By using the circuit and the method of the invention, a negative bias temperature instability, a positive bias temperature instability, hot hole injection or hot electron injection stress can be applied to pMOSFETs or nMOSFETs in a ring vibration inverter respectively; a ring oscillator is in a normal oscillation and stress oscillation state; the pMOSFETs or nMOSFETs of the inverter in the ring oscillator is in a measuring state of a charge pump. The degradation of the MOSFETs in the ring vibration inverter can be shown through changes of a ring oscillator oscillation frequency after the stress and can be shown through the changes of a CP current (Icpp or Icpn) of the pMOSFETs or nMOSFETs in the ring oscillator.

The invention relates to a flash memory structure, comprising: a substrate, a source region, a drain region and a channel region between the source region and the drain region are arranged in the substrate, and the substrate and the channel adopt P-type Impurity doping, the source region and the drain region are doped with high-concentration N-type impurities; and a tunnel oxide layer, a charge storage layer, a blocking oxide layer and a control gate layer are sequentially stacked on the base of the channel region. The present invention utilizes back gate bias to assist band tunneling hot hole injection for programming, hot holes can enter the charge storage layer under the condition of low voltage difference to realize programming, and the requirement for capacitive coupling coefficient is relatively low. The channel electron injection method is used for erasing, and the electrons in the channel can also enter the charge storage layer under the condition of low voltage difference, so that the holes and electrons are combined one by one, and the holes entering the charge storage layer are gradually erased during programming. holes, avoiding the problems of erasing saturation and process window reduction caused by the high-voltage FN erasing mechanism in the prior art.