253 results about "Charge loss" patented technology

A memory uses multiple threshold levels in a memory cell that are not a power of two, and further uses a cell mapping technique wherein the read mapping is only a partial function The domain of read states for a single three-level memory cell, for example, has three states, but only two of them can be uniquely mapped to a bit. The domain of read states for two three-level memory cell, for example, has nine states, but only eight of them can be uniquely mapped to three bits. Although the read mapping is only partial, the voltage margin for the three-level memory cells is larger that the voltage margin available in the commonly used four-level memory cells. This increased voltage margin facilitates memory cell threshold voltage sensing, thereby increasing the reliability of the memory. Memory reliability may be further improved by increasing the voltage margin between the memory cell 0 state and the 1 state relative to the voltage margin between the 1 state and the 2 state, which more effectively accommodates charge loss from the 0 state through electron leakage. Asymmetrical read and program mapping may also be used to improve read reliability in the presence of ground noise or VCC noise.

In a nonvolatile memory cell having a trap layer, programming or erasing is made in a sequence of first charge injection with a given wait time being secured and second charge injection executed after the first charge injection. Surrounding charge that deteriorates the data retention characteristic is reduced by use of initial variation occurring immediately after programming (charge loss phenomenon due to binding of injected charge with the surrounding charge in an extremely short time), and then the charge loss due to the initial variation is compensated, to thereby improve the data retention characteristic.

A method for detecting and predicting refrigerant level includes the steps of determining an estimated value for a parameter indicative of refrigerant level and comparing that estimated value to an actual value. The difference between the actual and estimated value provides a refrigerant charge indicator value. The charge indicator value is indicative of the amount of refrigerant contained within the system. A change value is combined with the charge indicator value to provide a prediction for the future value of the charge indicator value. This future value is determined based on a rate of change and charge indicator value over a selected period of time.

A refrigerant system has a controller associated with it that determines an equilibrium pressure when the system is inactive. The controller determines if the equilibrium pressure differs from an expected equilibrium pressure corresponding to a current ambient temperature and the selected refrigerant type. When the difference exceeds a selected threshold, the controller determines that the amount of refrigerant within the circuit is below a desired level. In one example, the controller provides an indication of a low charge amount. The disclosed technique allows early detection of refrigerant charge loss and differentiation between loss-of-charge and other failure modes. Consequently, system performance is enhanced, component damage is prevented, service interruptions and maintenance are reduced, exhaustive troubleshooting is avoided and potential exposure to refrigerant substances is minimized.

Ferroelectric memory cells (3) are presented, in which a cell resistor (R) is integrated into the cell capacitor (C) to inhibit charge accumulation or charge loss at the cell storage node (SN) when the cell (3) is not being accessed while avoiding significant disruption of memory cell access operations. Methods (100, 200) are provided for fabricating ferroelectric memory cells (3) and ferroelectric capacitors (C), in which a parallel resistance (R) is integrated in the capacitor ferroelectric material (20) or in an encapsulation layer (46) formed over the patterned capacitor structure (C).

Methods and systems for accurately programming or erasing one or more memory cells on a selected wordline of a memory device are provided. In one embodiment, the memory device comprises a memory array, a threshold voltage measuring component configured to measure a threshold voltage of each memory cell on the selected wordline of the memory array, and an average threshold voltage determining component configured to determine an average threshold voltage result uniquely associated with the selected wordline, based on the measured threshold voltages. The memory device is configured to program one or more of the memory cells to a predefined program level relative to the determined average threshold voltage, or to erase memory cells of the selected wordline to the determined average threshold voltage. The method is particularly useful for multi-level flash memory cells to reduce charge loss while improving data reliability and Vt distributions of the programmed element states.