97results about How to "Low budget" patented technology

A device having thin-film transistor (TFT) floating gate memory cell structures is provided. The device includes a substrate, a dielectric layer on the substrate, and one or more source or drain regions being embedded in the dielectric layer. the dielectric layer being associated with a first surface. Each of the one or more source or drain regions includes an N+ polysilicon layer on a diffusion barrier layer which is on a first conductive layer. The N+ polysilicon layer has a second surface substantially co-planar with the first surface. Additionally, the device includes a P− polysilicon layer overlying the co-planar surface and a floating gate on the P− polysilicon layer. The floating gate is a low-pressure CVD-deposited silicon layer sandwiched by a bottom oxide tunnel layer and an upper oxide block layer. Moreover, the device includes at least one control gate made of a P+ polysilicon layer overlying the upper oxide block layer. A method of making the same memory cell structure is provided and can be repeated to integrate the structure three-dimensionally.

The present invention provides an antenna array structure which includes multiple array elements, and the antenna array structure is using for the application of the WLAN (wireless local area network) or WMAN (wireless metro area network.) Furthermore, the array elements of the present invention are phased arrays or attenuated arrays, and when configuration with different type of the array element is used, the corresponding BFN (beam forming network) can also be implemented in various possibilities. With all the configuration of the present invention, the manufacturers can have a stable array structure for their applications.

A process for fabrication of a semiconductor device including an ONO structure as a component of a flash memory device, comprising forming the ONO structure by providing a semiconductor substrate having a silicon surface; forming a first oxide layer on the silicon surface; depositing a silicon nitride layer on the first oxide layer; and forming a top oxide layer on the silicon nitride layer, wherein the top oxide layer is formed by an in-situ steam generation oxidation of a surface of the silicon nitride layer. The semiconductor device may be, e.g., a SONOS two-bit EEPROM device or a floating gate FLASH memory device including an ONO structure.

Semiconductor devices, structures and systems that utilize a polysilazane-based silicon oxide layer or fill, and methods of making the oxide layer are disclosed. In one embodiment, a polysilazane solution is deposited on a substrate and processed with ozone in a wet oxidation at low temperature to chemically modify the polysilazane material to a silicon oxide layer.

Semiconductor devices, structures and systems that utilize a polysilazane-based silicon oxide layer or fill, and methods of making the oxide layer are disclosed. In one embodiment, a polysilazane solution is deposited on a substrate and processed with ozone in a wet oxidation at low temperature to chemically modify the polysilazane material to a silicon oxide layer.

Process for reducing charge leakage in a SONOS flash memory device, including in one embodiment, forming a bottom oxide layer of an ONO structure on the semiconductor substrate to form an oxide / silicon interface having a first oxygen content adjacent the oxide / silicon interface; treating the bottom oxide layer to increase the first oxygen content to a second oxygen content adjacent the oxide / silicon interface; and depositing a nitride charge-storage layer on the bottom oxide layer. In another embodiment, process for reducing charge leakage in a SONOS flash memory device, including forming a bottom oxide layer of an ONO structure on a surface of the semiconductor substrate having an oxide / silicon interface with a super-stoichiometric oxygen content adjacent the oxide / silicon interface; and depositing a nitride charge-storage layer on the bottom oxide layer.

A method is provided for forming a low-temperature vertical gate insulator in a vertical thin-film transistor (V-TFT) fabrication process. The method comprises: forming a gate, having vertical sidewalls and a top surface, overlying a substrate insulation layer; depositing a silicon oxide thin-film gate insulator overlying the gate; plasma oxidizing the gate insulator at a temperature of less than 400° C., using a high-density plasma source; forming a first source / drain region overlying the gate top surface; forming a second source / drain region overlying the substrate insulation layer, adjacent a first gate sidewall; and, forming a channel region overlying the first gate sidewall, in the gate insulator interposed between the first and second source / drain regions. When the silicon oxide thin-film gate insulator is deposited overlying the gate a Si oxide layer, a low temperature deposition process can be used, so that a step-coverage of greater than 65% can be obtained.

Process for fabricating a SONOS flash memory device, including in one embodiment, forming a bottom oxide layer of an ONO structure on a semiconductor substrate, wherein the bottom oxide layer has a first oxygen vacancy content; treating the bottom oxide layer to decrease the first oxygen vacancy content to a second oxygen vacancy content; and depositing a dielectric charge-storage layer on the bottom oxide layer. In another embodiment, a process for fabricating a SONOS flash memory device includes forming a bottom oxide layer of an ONO structure on the semiconductor substrate under strongly oxidizing conditions, wherein the bottom oxide layer has a super-stoichiometric oxygen content and an oxygen vacancy content reduced relative to a bottom oxide layer formed by a conventional process; and depositing a dielectric charge-storage layer on the bottom oxide layer.

Manufacturing a semiconductor device involves forming (200) a sacrificial layer where a micro cavity is to be located, forming (210) a metal layer of thickness greater than 1 micron over the sacrificial layer, forming (220) a porous layer from the metal layer, the porous layer having pores of length greater than ten times their breadth, and having a breadth in the range 10 nm-500 nanometers. The pores can be created by anodising, electrodeposition or dealloying. Then the sacrificial layer can be removed (230) through the porous layer, to form the micro cavity, and pores can be sealed (240). Encapsulating MEMS devices with a porous layer can reduce costs by avoiding using photolithography for shaping the access holes since the sacrificial layer is removed through the porous membrane.

A thin-film transistor (TFT) with a multilayer gate insulator is provided, along with a method for forming the same. The method comprises: forming a channel, first source / drain (S / D) region, and a second S / D region in a Silicon (Si) active layer; using a high-density plasma (HDP) source, growing a first layer of Silicon oxide (SiOx) from the Si active layer, to a first thickness, where x is less than, or equal to 2; depositing a second layer of SiOx having a second thickness, greater than the first thickness, overlying the first layer of SiOx; using the HDP source, additionally oxidizing the second layer of SiOx, wherein the first and second SiOx layers form a gate insulator; and, forming a gate electrode adjacent the gate insulator. In one aspect, the second Si oxide layer is deposited using a plasma-enhanced chemical vapor deposition (PECVD) process with tetraethylorthosilicate (TEOS) precursors.

In an embodiment, a method of forming a capacitor for a semiconductor device of which structural stability is improved is shown. Cylindrical storage electrodes are formed in a matrix pattern on a substrate that includes an insulation interlayer having contacts therein so that a mold layer surrounds the cylindrical storage electrodes. Sacrificial plugs are formed with a cap within these electrodes. A stabilizing layer is formed on the etched mold layer and the cylindrical storage electrode by partially etching the mold layer. The stabilizing layer is etched until the sacrificial plug is exposed, thereby forming a spacer. While the sacrificial plug and the mold layer are fully removed, the spacer is partially removed, thereby forming a stabilizing member for supporting neighboring storage electrodes adjacent to each other. Accordingly, a structural stability of the capacitor is improved.

A SONOS flash memory device, including a semiconductor substrate; an ONO structure formed on the semiconductor substrate, the ONO structure including a bottom oxide layer, a dielectric charge storage layer and a top oxide layer, the bottom oxide layer having a super-stoichiometric oxygen content and an oxygen vacancy content of about 1010 / cm2 or less, wherein the bottom oxide layer exhibits a reduced charge leakage relative to a bottom oxide layer having a stoichiometric or sub-stoichiometric oxygen content and a greater number of oxygen vacancies. In one embodiment, the bottom oxide layer has an oxygen vacancy content of substantially zero.

A heat pipe cooling system comprising an evaporator, a pipeline, a working fluid and a thermal connector is provided. The evaporator is connected to a heat-generating element, and the pipeline is connected to the evaporator. The working fluid is injected into a closed loop formed by the evaporator and the pipeline. The thermal connector comprises a first thermal conductive block and a second thermal conductive block. The first thermal conductive block has many first fitting parts and a contact surface. The contact surface is suitable for attaching to one of the surfaces of an object. The second thermal conductive block has many second fitting parts. The second fitting parts are suitable for meshing with the first fitting parts to form a piping channel inside the thermal connector. The piping channel is suitable for enclosing a section of the pipeline or directly serving as a part of the pipeline.

A method is provided for forming a Si and Si—Ge thin films. The method comprises: providing a low temperature substrate material of plastic or glass; supplying an atmosphere; performing a high-density (HD) plasma process, such as an HD PECVD process using an inductively coupled plasma (ICP) source; maintaining a substrate temperature of 400 degrees C., or less; and, forming a semiconductor layer overlying the substrate that is made from Si or Si-germanium. The HD PECVD process is capable of depositing Si at a rate of greater than 100 Å per minute. The substrate temperature can be as low as 50 degrees C. Microcrystalline Si, a-Si, or a polycrystalline Si layer can be formed over the substrate. Further, the deposited Si can be either intrinsic or doped. Typically, the supplied atmosphere includes Si and H. For example, an atmosphere can be supplied including SiH4 and H2, or comprising H2 and Silane with H2 / Silane ratio in the range of 0-100.

Methods are provided for forming silicon dioxide (SiO2) on a silicon carbide (SiC) substrate. The method comprises: providing a SiC substrate; supplying an atmosphere including oxygen; performing a high-density (HD) plasma-based process; and, forming a SiO2 layer overlying the SiC substrate. Typically, performing the HD plasma-based process includes connecting a top electrode to an inductively coupled HD plasma source. In one aspect, SiO2 is grown on the SiC substrate. Then, an HD plasma oxidation process is performed that creates a reactive oxygen species and breaks the Si—C bonds in the SiC substrate, to form free Si and C atoms in the SiC substrate. The free Si atoms in the SiC substrate are bonded to the HD plasma-generated reactive oxygen species, and the SiO2 layer is grown.

A method for forming an L-shaped spacer using a sacrificial organic top coating. A semiconductor structure is provided having a gate structure thereon. A liner oxide layer is formed on the gate structure. A dielectric spacer layer is formed on the liner oxide layer. In the preferred embodiment, the dielectric spacer layer comprises a silicon nitride layer or a silicon oxynitride layer. A sacrificial organic layer is formed on the dielectric spacer layer. The sacrificial organic layer and the dielectric spacer layer are anisotropically etched to form spacers comprising a triangle-shaped sacrificial organic structure and an L-shaped dielectric spacer. The triangle-shaped sacrificial organic structure is removed leaving an L-shaped dielectric spacer.

An electrical switch using a gated resistor structure includes an isolation layer, a doped silicon layer arranged on the isolation layer and having a recessed portion with reduced thickness, the doped silicon layer having a predetermined doping type and a predetermined doping profile; a gate layer arranged corresponding to the recessed portion. The recessed portion in the doped silicon layer has such thickness that a channel defined under the gate can be fully depleted to form a high resistivity region. The recessed channel gated resistor structure can be advantageously used to achieve high interconnect density with low thermal budget for 3D integration.

A precursor for forming a thin film of layered superlattice material is applied to an integrated circuit substrate. The precursor coating is heated using rapid thermal processing (RTP) with a ramping rate of 100° C. / second at a hold temperature in a range of from 500° C. to 900° C. for a cumulative heating time not exceeding 30 minutes, and preferably less than 5 minutes. In fabricating a ferroelectric memory cell, the coating is heated in oxygen using RTP, then a top electrode layer is formed, and then the substrate including the coating is heated using RTP in oxygen or in nonreactive gas after forming the top electrode layer. The thin film of layered superlattice material preferably comprises strontium bismuth tantalate or strontium bismuth tantalum niobate, and preferably has a thickness in a range of from 25 nm to 120 nm. The process of fabricating a thin film of layered superlattice material typically has a thermal budget value not exceeding 960,000° C.-sec, preferably less than 50,000° C.-sec.

Methods and systems for encouraging and identifying new talent, as well as an incentive structure for financing creative / media projects, are described. A social network web site allows users to post their own content, and filters users to the top who have achieved a given level of popularity. Popular users can then post media proposals to a private section of the web site, through which established stars and talent review the proposals. Users, in exchange for access to the private section, grant to a proprietor of the web site an option to make one or more future productions with that user at a reduced rate should that user reach stardom. Established stars and talent, in exchange for participating in a media proposal at a reduced rate, receive an interest in one or more productions by the user if / when the proprietor of the web site exercises an option to make a future production with the user.

The present invention provides a stabilized fine textured metal microstructure that constitutes a durable activated surface usable for bonding a 3D stacked chip. A fine-grain layer that resists self anneal enables metal to metal bonding at moderate time and temperature and wider process flexibility.

Reliable HTO (High Temperature Oxide) dielectrics are provide by a rapid thermal chemical vapor deposition (RTCVD) process in which a low pressure and a high ratio of reactants, e.g., oxygen-containing gas to silane-containing gas, is employed. Specifically, the reliable HTO is formed by a rapid thermal chemical vapor deposition at temperatures of from about 500° C. or above, said rapid thermal chemical vapor deposition process being carried out at a pressure of less than 80 Torr and in the presence of at least one oxygen-containing reactant and at least one silane-containing reactant, said reactants having a ratio of oxygen-containing to silane-containing of about 25:1 or greater. Semiconductor devices such as capacitors and transistors that include at least a layer of the high temperature oxide of the present invention used as a dielectric material are also provided.

A high-density plasma hydrogenation method is provided. Generally, the method comprises: forming a silicon (Si) / oxide stack layer; plasma oxidizing the Si / oxide stack at a temperature of less than 400° C., using a high density plasma source, such as an inductively coupled plasma (ICP) source; introducing an atmosphere including H2 at a system pressure up to 500 milliTorr; hydrogenating the stack at a temperature of less than 400 degrees C., using the high density plasma source; and forming an electrode overlying the oxide. The electrode may be formed either before or after the hydrogenation. The Si / oxide stack may be formed in a number of ways. In one aspect, a Si layer is formed, and the silicon layer is plasma oxidized at a temperature of less than 400 degrees C., using an ICP source. The oxide formation, additional oxidation, and hydrogenation steps can be conducted in-situ in a common chamber.

Manufacturing a semiconductor device involves forming (200) a sacrificial layer where a micro cavity is to be located, forming (210) a metal layer of thickness greater than 1 micron over the sacrificial layer, forming (220) a porous layer from the metal layer, the porous layer having pores of length greater than ten times their breadth, and having a breadth in the range 10 nm-500 nanometers. The pores can be created by anodising, electrodeposition or dealloying. Then the sacrificial layer can be removed (230) through the porous layer, to form the micro cavity, and pores can be sealed (240). Encapsulating MEMS devices with a porous layer can reduce costs by avoiding using photolithography for shaping the access holes since the sacrificial layer is removed through the porous membrane.

A method of manufacturing a MOS transistor is provided. A substrate having a gate structure thereon is provided. A first spacer is formed on the sidewall of the gate structure. A pre-amorphization implantation is carried out to amorphize a portion of the substrate. A doped source / drain extension region is formed in the substrate on each side of the first spacer. A second spacer is formed on the sidewall of the first spacer. A doped source / drain region is formed in the substrate on each side of the second spacer and then a pre-annealing operation is performed. Thereafter, a solid phase epitaxial process is carried out to re-crystallize the amorphized portion of the substrate and activate the doped source / drain extension region and the doped source / drain region to form a source / drain terminal. Finally, a post-annealing operation is performed.

By using a combination of solid phase epitaxy re-growth and laser annealing, the present invention provides a low thermal budget method which allows the crystal lattice of a semiconductor surface to recover after the doping by ion implantation. The low thermal budget limits the out-diffusion of the dopants ions, thus avoiding the enlargement of the doped source / drain regions. Therefore, the method is suited, for instance, for the fabrication of ultra-shallow source / drain regions in MOS transistors elements. The method according to the present invention comprises a first pre-amorphization process in order to limit channeling effects, a doping process by ion implantation and a re-crystallization by solid phase epitaxy, followed by laser annealing.

A method of manufacturing a MOS transistor is provided. A substrate having a gate structure thereon is provided. A first spacer is formed on the sidewall of the gate structure. A pre-amorphization implantation is carried out to amorphize a portion of the substrate. A doped source / drain extension region is formed in the substrate on each side of the first spacer. A second spacer is formed on the sidewall of the first spacer. A doped source / drain region is formed in the substrate on each side of the second spacer and then a pre-annealing operation is performed. Thereafter, a solid phase epitaxial process is carried out to re-crystallize the amorphized portion of the substrate and activate the doped source / drain extension region and the doped source / drain region to form a source / drain terminal. Finally, a post-annealing operation is performed.

Silicon oxynitride compositions are described herein. These compositions are typically deposited onto substrates using a nitrogen plasma-based, reactive sputtering method. Depending on their composition, these coatings can be used for field emission suppression, dielectric applications, reflection control, and surface passivation.

Methods are provided for forming silicon dioxide (SiO2) on a silicon carbide (SiC) substrate. The method comprises: providing a SiC substrate; supplying an atmosphere including oxygen; performing a high-density (HD) plasma-based process; and, forming a SiO2 layer overlying the SiC substrate. Typically, performing the HD plasma-based process includes connecting a top electrode to an inductively coupled HD plasma source. In one aspect, SiO2 is grown on the SiC substrate. Then, an HD plasma oxidation process is performed that creates a reactive oxygen species and breaks the Si—C bonds in the SiC substrate, to form free Si and C atoms in the SiC substrate. The free Si atoms in the SiC substrate are bonded to the HD plasma-generated reactive oxygen species, and the SiO2 layer is grown.