111results about How to "Excellent gap filling" patented technology

A semiconductor device having metal gate includes a substrate, a first metal gate positioned on the substrate, and a second metal gate positioned on the substrate. The first metal gate includes a first work function metal layer, and the first work function metal layer includes a taper top. The second metal gate includes a second work function metal layer. The first work function metal layer and the second work function metal layer are complementary to each other.

A method for forming an L-shaped spacer using disposable polysilicon top spacers. A semiconductor structure is provided having a gate structure thereon. A liner oxide layer is formed on the gate structure. A dielectric spacer layer is formed on the liner oxide layer. A disposable polysilicon top spacer layer is formed on the dielectric spacer layer. The disposable polysilicon top spacer layer is anisotropically etched to form disposable polysilicon top spacers. The dielectric spacer layer is etched to form L-shaped dielectric spacers, using the disposable polysilicon top spacers as an etch mask. The disposable polysilicon top spacers are removed leaving an L-shaped dielectric spacer. In one embodiment, lightly doped source and drain regions are formed prior to forming the liner oxide layer and the L-shaped spacers.

The present invention relates to a method for fabricating a semiconductor device with realizable advanced fine patterns. The method includes the steps of: forming a hard mask insulation layer on an etch target layer; forming a hard mask sacrificial layer on the hard mask insulation layer; coating a photoresist on the hard mask insulation layer; performing selectively a photo-exposure process and a developing process to form a photoresist pattern having a first width for forming a line pattern; etching selectively the hard mask sacrificial layer by using the photoresist pattern as an etch mask to form a sacrificial hard mask having a second width; removing the photoresist pattern; etching the hard mask insulation layer by controlling excessive etching conditions with use of the sacrificial hard mask as an etch mask to form a hard mask having a third width; and etching the etch target layer by using the sacrificial hard mask and the hard mask as an etch mask to form the line pattern having a fourth width, wherein the first width is wider than the fourth width.

A method for forming an L-shaped spacer using a sacrificial organic top coating. A semiconductor structure is provided having a gate structure thereon. A liner oxide layer is formed on the gate structure. A dielectric spacer layer is formed on the liner oxide layer. In the preferred embodiment, the dielectric spacer layer comprises a silicon nitride layer or a silicon oxynitride layer. A sacrificial organic layer is formed on the dielectric spacer layer. The sacrificial organic layer and the dielectric spacer layer are anisotropically etched to form spacers comprising a triangle-shaped sacrificial organic structure and an L-shaped dielectric spacer. The triangle-shaped sacrificial organic structure is removed leaving an L-shaped dielectric spacer.

A method of fabricating a dielectric layer includes the following steps. At first, a dielectric layer is formed on a substrate, and a chemical mechanical polishing (CMP) process is performed on the dielectric layer. Subsequently, a surface treatment process is performed on the dielectric layer after the chemical mechanical polishing process, and the surface treatment process includes introducing an oxygen plasma.

The method for manufacturing an STI in a semiconductor device with an enhanced gap-fill property and leakage property is disclosed by introducing a nitridation process instead of forming a liner nitride. The method includes steps of: preparing a semiconductor substrate obtained by a predetermined process on which a pad oxide and a pad nitride are formed on predetermined locations thereof; forming an isolation trench with a predetermined depth in the semiconductor substrate; forming a wall oxide on the trench; forming a liner oxide on the wall oxide and an exposed surface of the pad nitride; carrying out a nitridation process for forming a nitrided oxide; forming an insulating layer over the resultant structure, wherein the isolation trench is filled with the insulating layer; and planarizing a top face of the insulating layer.

A thin film comprising a composition obtained by polymerizing a monomer having the formula I:

wherein:

• • R₁ is a hydrolysable group,
  • R₂ is a polarizability reducing organic group, and
  • R₃ is a bridging hydrocarbon group, to form a siloxane material. The invention also concerns methods for producing the thin films. The thin film can be used a low k dielectric in integrated circuit devices. The novel dielectric materials have excellent properties of planarization resulting in good local and global planarity on top a semiconductor substrate topography, which reduces or eliminates the need for chemical mechanical planarization after dielectric and oxide liner deposition.

The invention relates to a collecting pipe material for a micro-channel heat exchanger, which consists of a layer of brazing layer alloy and a layer of matrix alloy, wherein the brazing layer alloy comprises the following components in percentage by weight: 9-11% of Si, 0.2-0.4% of Fe, 0.005-0.05% of Cu, 0.005-0.05% of Mn, 0.005-0.05% of Mg, 0.005-0.05% of Cr, 0.3-0.7% of Zn, 0.005-0.05% of Zr, 0.005-0.10% of Ti and the balance of A1; the preparation method of the brazing layer alloy comprises the processes of casting, modifying and founding; the preparation method of the matrix alloy comprises the processes of casting, founding and homogenizing; processes of compositing, hot rolling, cold rolling and intermediate annealing are carried out on the brazing layer alloy and the matrix alloy to obtain the collecting pipe material; the brazing layer alloy has favorable grain refining effect so that favorable fluidity, wettability and gap filling capability are provided during the brazing of the material; cold machining is carried out on the material with a machining rate of 25-35% after the intermediate annealing treatment; and the machining rate can ensure that the forming property is favorable during the pipe making of the material and the fluidity of the brazing layer is favorable during the brazing of the collecting pipe.

A hot-melt silicone adhesive comprising: (A) an organopolysiloxane resin with a softening point in the range of 40 to 250° C.; (B) an organopolysiloxane that at 25° C. is liquid or in the state of a crude rubber, which contains in one molecule at least two alkenyl groups; (C) a composition selected from a mixture of (i) an organopolysiloxane that contains silicon-bonded hydrogen atoms and (ii) an organic silicon compound that contains a silicon-bonded alkoxy group; or (iii) an organopolysiloxane that contains silicon-bonded hydrogen atoms and a silicon-bonded alkoxy group; (D) a hydrosilylation catalyst; and (E) a hydrosilylation-reaction inhibitor, demonstrates good gap-filling ability during thermo-compressive bonding to adherends with high surface roughness, even at low pressures, and that provides strong adhesion to the adherend after cross-linking.