A modular signal processing flow graph and multiprocessor hardware platform modeling method is characterized by being a modeling method of mapping modular signal processing flow graphs to a multiprocessor hardware platform. The method comprises three parts of a signal flow graph system, a hardware platform system and a mapping system. Firstly, the modular signal processing flow graphs are modeled, that is, a module system and a data stream system are modeled respectively, the former is used for modeling all functional modules in the flow graphs, and the latter is used for modeling data communication relations among all modules in the flow graphs. Secondly, the multiprocessor hardware platform is modeled, that is, an internal-node system and an among-node system are modeled respectively, the former is used for modeling a processor system of single node and interconnection topology among processors in the nodes, and the latter is used for modeling overall attribute of single node and topology structures among the nodes. And finally, the mapping system is modeled to achieve mapping relations between the modules in the flow graphs and cores of the processors.