Logic expression extraction and switch level design method of CMOS transmission gate logic circuit

A logic expression, logic circuit technology, applied in computing, electrical digital data processing, special data processing applications, etc., can solve the problems of reduced process feature size and increased static power consumption of MOS transistors

Active Publication Date: 2019-09-20
HUAIBEI NORMAL UNIVERSITY
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Problems solved by technology

[0016] (2) The power supply voltage of the circuit is reduced, which reduces the dynamic power consumption; but the process feature size is reduced, so that the threshold voltage of the MOS transistor and the thickness of the gate oxide layer are correspondingly reduced, and the subthreshold value generated by the subthreshold (weak inversion) conduction of the

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  • Logic expression extraction and switch level design method of CMOS transmission gate logic circuit
  • Logic expression extraction and switch level design method of CMOS transmission gate logic circuit
  • Logic expression extraction and switch level design method of CMOS transmission gate logic circuit

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Embodiment 1

[0075] A logical expression extraction and switch-level design method for a CMOS transmission gate logic circuit expands the Boolean algebra system to obtain an extended Boolean algebra system; a corresponding switch-level signal flow graph model is established by the CMOS transmission gate logic circuit, thereby The equivalent signal flow graph model of the output function of the circuit is extracted from the model, and the switch-level function expression of the circuit is obtained by combining the switch-level signal flow graph model with the extended Boolean algebra system, and thus the CMOS transmission gate logic circuit is obtained.

[0076] The number of MOS tubes contained in the circuit is still an important indicator to measure the power consumption and area of ​​the circuit. The study found that using the full-swing CMOS transmission gate circuit structure can avoid threshold voltage loss, reduce sub-threshold power consumption, and reduce the number of MOS transist...

Embodiment 2

[0115] Such as figure 1 As shown, there are four types of component branches of the CMOS transmission gate circuit, namely, the PMOS tube branch, the NMOS tube branch, the CMOS transmission gate branch and the connection branch, wherein the PMOS tube and the NMOS tube are single-channel transmission gates, The 1 signal and the 0 signal can be transmitted without loss, respectively, and the CMOS transmission gate branch is a dual-channel transmission gate, which can transmit signal variables without loss. The above three types of branches are all controlled branches, and the connection branches are uncontrolled branches, that is, direct transmission (through) branches. The switch-level function expressions of the four types of component branches are respectively

[0116] f1 =x 0.5 ·[1],f 2 = 0.5 x[0], f 4 =U·[y]=[y]

[0117] Its corresponding switch-level signal flow graph model, such as figure 2 shown. The arrow on the branch indicates the transmission (flow) direct...

Embodiment 3

[0128] Such as Figure 7 As shown, the CMOS transmission gate type full adder circuit (the circuit name is EX2) obtained by using the switch-signal theory design method. Use the equivalent signal flow graph model method to find the logic function expression of the circuit.

[0129] Step1 modeling. Depend on Figure 7 For the full adder circuit shown, draw the signal flow graph model of the complement function of the output function of the circuit as Figure 8 shown. In the figure, C(0) means C=0, express etc. Depend on Figure 8 ,use and The signal flow diagram of the transmission 0 signal is transformed to obtain the output function s of the circuit i , c i and the equivalent signal flow graph model of h as Figure 9 shown.

[0130] Step2 analysis. Depend on Figure 9 The output s of the full adder can be obtained directly i and c i for

[0131]

[0132] After simplification by Boolean algebra (signal algebra) method, the logical expression of the ful...

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Abstract

The invention discloses a logic expression extraction and switch level design method for a CMOS transmission gate logic circuit, and the method comprises the steps: carrying out the expansion of a Boolean algebra system, and obtaining an expanded Boolean algebra system; a CMOS transmission gate logic circuit establishing a corresponding switch level signal flow graph model; extracting the equivalent signal flow graph model of the circuit output function by the model, and obtaining the switch-level function expression of the circuit by combining the switch-level signal flow graph model with an extended Boolean algebra system, so that the CMOS transmission gate logic circuit is obtained. According to the CMOS transmission gate logic circuit designed through the method, the number of required MOS tubes is small, the number of required connection wires is small, power consumption can be reduced, and the chip area can be saved; and the designed switch level CMOS transmission gate logic circuit is full in swing amplitude, and is suitable for the design of a low-power consumption CMOS circuit.

Description

technical field [0001] The invention relates to a logic expression extraction and switch level design method of a logic circuit, in particular to a logic expression extraction and switch level design method of a CMOS transmission gate logic circuit. Background technique [0002] Complementary metal-oxide semiconductor (CMOS) integrated circuits are widely used in very large-scale integrated circuits (VLSI) because of their low power consumption, high integration, strong anti-interference ability, and wide power supply voltage range. Among them, logic circuits composed of various combinations of CMOS transmission gates have become a wider circuit form. Studies have shown that a simpler circuit structure can often be obtained by using the switch-level design method. This circuit structure is a CMOS transmission gate logic circuit composed of various combinations of CMOS transmission gates. [0003] However, how to extract the corresponding logic functions from the actual or d...

Claims

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Application Information

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IPC IPC(8): G06F17/50
CPCG06F30/39G06F30/20
Inventor 姜恩华
Owner HUAIBEI NORMAL UNIVERSITY
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