51results about How to "High speed action" patented technology

A lens shutter system has an inner drive ring which is rotated by a drive motor and an outer drive ring which is rotated by the drive motor. A plurality of shutter blades of the lens shutter system are driven through drive pins of the inner drive ring and drive pins of the outer drive ring so as to be opened and closed or are rotatably supported by the respective pins of the rings. Upon shutter opening, only the inner drive ring is driven clockwise to open the shutter blades. Upon shutter closing, only the outer drive ring is similarly driven clockwise to close the shutter blades. As mentioned above, upon switching between shutter opening mode and shutter closing mode, the direction of rotation of the inner and outer drive rings is not changed. Thus, the shutter operation can be performed at high speed.

The present invention provides a reciprocating insertion device capable of inserting contents into a large number of bag bodies in a reduced time. The reciprocating insertion device (1), in a process in which bag bodies (3) having openings (2) are conveyed in a conveying direction (T), inserts contents (4) into the openings (2). The reciprocating insertion device (1) is provided with a moving means (6) for moving, in synchronism with the speed at which the bag bodies (3) are conveyed, the contents (4) in an attitude in which the contents (4) face the bag bodies (3), an in-and-out means (8) for advancing and retracting guide horns relative to the bag bodies (3), the guide horns guiding the contents (4) to the openings (2) of the bag bodies (3), an advancing and retracting means (7) for advancing and retracting pushers relative to the bag bodies (3), the pushers pushing out the contents (4) from the moving means (6) to the openings (2) of the bag bodies (3), and a reciprocating means (9) for moving forward or in the opposite direction the in-and-out means (8) and the advancing and retracting means (7) in the conveying direction (T) at the conveying speed. In the process in which the reciprocating means (9) moves forward the in-and-out means (8) and the advancing and retracting means (7), the in-and-out means (8) and the advancing and retracting means (7) perform the following operations. That is, the operations by the in-and-out means (8) are an operation in which the in-and-out means (8) advances the guide horns until the guide horns enter the openings (2) of the bag bodies (3) and an operation in which the in-and-out means (8) retracts the guide horns from the bag bodies (3).

By arranging a dummy cell array (201) in a memory array (101), and an intermediate buffer (300) between input / output circuits (400), control signals of the input / output circuits (400) can be operated at a high speed and a high frequency, while minimizing increase in circuit size even for memory having a wide bit-width.

The present invention aims to provide a differential amplifier circuit that prevents degradation of performance and that can be overdrive recovered even if a power supply voltage is relatively small. PMOS transistors are interposed parallel to each other between a node, which is a first output part, and a power supply; and PMOS transistors are interposed in parallel to each other between a node, which is a second output part, and the power supply. Output voltages in time of a balanced state in which an input potential difference between an input voltage and a reference voltage is '0' are bothset to a reference output common voltage by a replica circuit and a comparator. The reference output common voltage of the replica circuit is set so that the potential difference between the power supply voltage and the output common voltage becomes a value lower than a threshold voltage of the diode connected PMOS transistors.

A level shift circuit which realizes a high-speed and power-saved operation particularly when the input voltage is at a low level is provided. The level shift circuit of the present invention comprises a first gate voltage control circuit controlled by a inverted signal of an input signal, which is inserted between a gate of a third transistor and a second output terminal; a second gate voltage control circuit controlled by the input signal, which is inserted between a gate of a fourth transistor and a first output terminal; a first transistor; and a second transistor. When the input signal shifts from 'H' to 'L', the first transistor turns OFF, the third transistor is turned ON by the first gate voltage control circuit, and then a voltage of the first output terminal rises. The second transistor turns ON, the fourth transistor is turned OFF by the second gate voltage control circuit, and then the voltage of the second output terminal goes down.

The semiconductor device of the present invention includes a semiconductor layer (10-15), a gate insulating film (16) provided on the semiconductor layer, a gate electrode (17) provided on the gate insulating film, and in the semiconductor layer A source region (20a) and a drain region (20b) of the first conductivity type provided on both sides of the gate electrode are viewed from a plan view, and between the source region and the drain region in the semiconductor layer, The gap layer (25), the channel region (24) and the region below the channel (23, 22) of the second conductivity type arranged in sequence downward from the interface with the above-mentioned gate insulating film, and the application to the above-mentioned channel below the region A bias electrode part (Vbs) for voltage, wherein the channel region is composed of a first semiconductor, and the gap layer and the region below the channel are respectively composed of a second semiconductor and a third semiconductor having a band gap larger than that of the first semiconductor, The above-mentioned bias electrode member is provided independently of the above-mentioned gate electrode and capable of applying a voltage.

The invention relates to an optical sensor and an electronic device. When no light enters a photodiode, a second current mirror circuit operates. Consequently, a current that decreases a potential difference between two terminals of a light-receiving element flows into a transistor of the second current mirror circuit and an output of an optical sensor becomes low. Meanwhile, when light enters the photodiode, a transistor of the light-receiving element is turned on and the second current mirror circuit stops operating. Consequently, the current that decreases the potential difference between the two terminals of the light-receiving element is stopped in the transistor of the second current mirror circuit and the output of the optical sensor becomes high. This makes it possible to provide an optical sensor that has a circuit in which an output of a light-receiving element does not depend on a photocurrent and that is capable of operating at a high speed.

An MCM-type semiconductor device allowing high-speed operation and reduction in power consumption, and is also capable of preventing reliability and yield rate of MCM from degrading. The reduction in power consumption and increase in operation speed are attained by connecting signal lines between in-chip circuits (30), (32) in an electrically direct manner. On the signal line, a protection circuit (406) for electrostatic damage protection is provided. In device fabrication, connection using interconnections (12) between the in-chip circuits (30), (32) is carried out while keeping a protection circuit (406) connected to the signal lines (internal draw-out lines (12a), internal interconnections (14)), by which circuit components can be protected from static electricity even if electric charge accumulated on the semiconductor chips (20), (22) should flow into the signal lines, because the protection circuit (406) can absorb the charge. After the connection is completed, the protection circuit (406) can be disconnected from the signal lines, so as to avoid the protection circuit (406) to function as a load on the in-chip circuits (30), (32) during normal operation, and to thereby prevent the operation speed from decreasing.

A solid-state image pickup apparatus 1A includes a photodetecting section 10A, a signal readout section 20, and a controlling section 40A. In the photodetecting section 10A, M×N pixel units P 1,1 to P M,N each including a photodiode and a readout switch are arrayed in M rows and N columns. Charges generated in each pixel unit P m,n are input to an integrating circuit S n through a readout wiring L O,n , and a voltage value output from the integrating circuit S n in response to the charge amount is output through a holding circuits H n . When in a first imaging mode, a voltage value according to an amount of charges generated in the photodiode PD of each of the M×N pixel units P 1,1 to P M,N in the photodetecting section 10A is output from the signal readout section 20. When in a second imaging mode, a voltage value according to an amount of charges generated in the photodiode PD of each pixel unit P m,n included in consecutive M 1 rows in the photodetecting section 10A is output from the signal readout section 20.

The invention provides a level shift circuit, and a driver and a display device using the same. The level shift circuit includes a first circuit connected between a first power supply terminal (PST) and an output terminal (OT) of the level shift circuit to set OT to a first voltage (V1) when conducting, a second circuit connected between a second PST and OT to set OT to the second voltage (V2) when conducting, and a third circuit that receives an input signal and a feedback signal from OT so that, when OT=V2 and input=a third voltage (V3), the first circuit conducts, and when OT=V1, the first circuit is made nonconductive irrespective of the value of the input signal. The second circuit is made conductive and nonconductive when the reverse-phase signal of the input signal is equal to V3 and the reverse-phase signal of the input signal is equal to a fourth voltage (V4), wherein V2<=V4<V3<V1.

The invention discloses a tubular container end face sealing paper sheet transferring and overturning device which comprises a paper receiving mechanism and a paper sheet conveying mechanism, a plurality of overturning gears and suction cups are distributed on a paper receiving wheel of the paper receiving mechanism in the circumferential direction, and paper suction discs of the overturning gears and the suction cups can suck sealing paper sheets; a paper sheet conveying mechanism is arranged on the outer side of the paper receiving mechanism, and a plurality of paper suction assemblies are arranged on the paper sheet conveying mechanism; when the overturning gear, the suction cup and the paper suction assembly move to the paper sheet connecting area at the same time, the paper suction assembly delivers the sucked sealing paper sheets to the overturning gear and the suction cup. The overturning gear and the paper suction disc of the suction cup receive the sealing paper sheets delivered by the paper suction assembly, and the sealing paper sheets in the vertical state are overturned to be in the horizontal state. Through the same paper receiving mechanism, not only can the handover action of paper sheets be completed, but also the overturning of the paper sheets can be realized, and the equipment integration degree is high. The invention further discloses a connecting and overturning method of the tubular container end face sealing paper piece.

In order to achieve an object to reduce a surge voltage and suppress noise generation, the present invention provides a DC-DC converter with a snubber circuit, which boosts a voltage Vi of a DC power supply. The snubber circuit includes: a series circuit connected to both ends of a smoothing capacitor Co and including a snubber capacitor Cs and a snubber resistor Rs; a snubber diode Ds1 connected to a node at which the snubber capacitor Cs and the snubber resistor Rs are connected, and to a node at which a reactor Lr1 and an additional winding 1b of a transformer T1 are connected; and a snubber diode Ds2 connected to the node at which the snubber capacitor Cs and the snubber resistor Rs are connected, and to a node at which a reactor Lr2 and an additional winding 2b of a transformer T2 are connected.

A DRAM, including a plurality of banks each having a plurality of sub-arrays, and sense amplifier circuits commonly shared by sub-arrays in different banks, has a row access mode for activating a sub-array selected from each bank for reading or writing data, and a refresh mode for activating a plurality of sub-arrays in each bank and refreshing memory cell data therein at substantially the same timing. Sub-arrays in each bank activated at substantially the same timing in the refresh mode are more than sub-arrays in each bank activated in the row access model. Thereby, occurrence of operation constrains is minimized to ensure high-speed operation and improve the system performance of DRAMs employing the non-independent bank system.

A thin stacked semiconductor device suitable for high speed operation. A plurality of specified circuits are formed on one surface of a semiconductor substrate while being arranged, and wiring and insulating layers being connected electrically with the circuits are laminated and formed sequentially in a specified pattern to form a multilayer wiring part. At the stage for forming the multilayer wiring part, a filling electrode is formed on the semiconductor substrate such that the surface is covered with an insulating film, a post electrode is formed on specified wiring at the multilayer wiringpart, a first insulating layer is formed on one surface of the semiconductor substrate, the surface of the first insulating layer is removed by a specified thickness to expose the post electrode, theother surface of the semiconductor substrate is ground to expose the filling electrode and to form a through-type electrode, forward end of the through-type electrode is projected by etching one surface of the semiconductor substrate, a second insulating layer is formed on one surface of the semiconductor substrate while exposing the forward end of the through-type electrode, bump electrodes areformed on both electrodes and then the semiconductor substrate is divided to form a semiconductor device. A plurality of semiconductor devices thus obtained are stacked and secured at the bump electrodesthus manufacturing a stacked semiconductor device.

latch circuits and semiconductor memory devices. The latch circuit includes an input circuit including an input PMOS transistor that causes a signal current corresponding to the sensed voltage to flow; a first inverter including a first PMOS transistor, a first NMOS transistor, and a first node. The first PMOS transistor and the first NMOS transistor are connected and connected to the input circuit; and the second inverter includes a second PMOS transistor, a second NMOS transistor and a second node, the second node connects the second PMOS transistor and the second NMOS transistor. The first inverter and the second inverter are connected in cascade.

A pseudo random number generation device (100) generates a pseudo random number as follows. In C.2, S1[B41] is decided from B41 set in a second internal memory, and S2[B40] is decided from B40. R[J] is generated from S1[I], S1[B41], and S2[B40]. In C.3, S1[I] is newly generated according to S1[B41] and S2[B40]. In C.4, B4 is updated from S2(I). In the aforementioned process, the association of R[J] with S2(I) is cut off and it is difficult to estimate S2(I) from R[J], which increases the safety. Moreover, the S1[I], S1[B41], S2[B40], and the like are four-byte codes and processing speed can be increased.

A memory to which a bit line potential step-down technique is applied is provided. The memory includes an IO block including first transistors which control potentials of first bit lines provided with respect to columns of memory cells, and first logic gates which control the first transistors. The drain or source of each first transistor is connected to an input of the corresponding first logic gate, and the gate of each first transistor is connected to an output of the corresponding first logic gate. The first transistors are driven by pulses.