196results about "Switching accelaration modifications" patented technology

A current mode logic digital circuit is provided comprising a logic circuit component having at least one data input node and at least one output node. A load is coupled between a power supply node and the output node. The load comprises a folded active inductor coupled to the output node.

A method and apparatus for creating high speed logic circuits in a CMOS environment using current steering logic cells with actively-peaked NMOS or PMOS loads and the biasing of these logic cells is disclosed. The logic cells can include, for example, buffers, AND gates, OR gates, flip-flops, and latches. The current steering cells with actively-peaked loads can provide benefits such as reduced power consumption, smaller area, and higher speed performance over conventional devices. This performance boost is preferably achieved using NMOS followers with resistively degenerated gates to create frequency peaked transfer function of current-mode logic cells. These logic cells with actively-peaked loads can advantageously be used in circuits in which relatively good power area and performance are desired for state machine logic, parallel to serial conversions, serial to parallel conversions, and the like.

Systems and methods for enhancing slew control of output signals. An output driver receives an input signal and controllably increases the gain of that signal to provide a high quality output signal for use by an electronic device coupled thereto. The output driver includes an operational amplifier that maintains stability of the output signal through a feedback of the output signal. A control circuit supplies a signal to the output driver such that the driver to improve the shape of the output signal as the input signal is applied. After the operational amplifier regains control, the control circuit disengages. One embodiment of the present invention may be particularly useful as a USB output driver.

In addition to two-stage CMOS inverters inverting and amplifying the input signal, a rising edge detector detects the rising edge of the input signal, and outputs a rising edge detection signal having a pulse width corresponding to ambient temperature, a PMOS drives the output node to the power supply potential according to the rising edge detection signal, a falling edge detector detects the falling edge of the input signal and outputs a falling edge detection signal having a pulse width corresponding to ambient temperature, and an NMOS drives the output node to ground potential according to the falling edge detection signal. When ambient temperature rises, and delay time of the inverters are thereby increased, pulse widths of the rising and falling edge detection signals are increased. The additional driving restrains delay time variation in a driving circuit due to ambient temperature change.

In accordance with the invention, a driver circuit is described that permits a single thin gate oxide process to be utilized where a dual oxide process may normally be necessary. Circuits employing only thin gate oxide devices are used as the design basis for a single product with a single set of tooling and manufacturing process to operate within the same timing specifications for a core voltage output drive as well as for a higher system drive.

The invention relates to a line driver supplied with a power supply voltage from a power supply and an amplifying method. According to the invention the following steps are performed: using whole or part of the power supply voltage to generate the output voltage if the input voltage is within the predefined range; loading at least one capacitor with at least one capacitor voltage; and using whole or part of the capacitor voltage in addition to whole or part of the power supply voltage to generate the output voltage if the input voltage is outside the predefined range.

A semiconductor integrated circuit comprises a semiconductor chip, a power supply terminal provided on the semiconductor chip for receiving a voltage from an external power supply source, an internal circuit provided on the semiconductor chip, a power supply circuit provided on the semiconductor chip for transforming an external power supply voltage received from the power supply terminal for supplying a source voltage resulting from the voltage transformation to the internal circuit, and a control circuit provided on the semiconductor chip for controlling the power supply circuit, wherein the control circuit includes external power supply voltage detecting means and / or temperature detecting means and responds to the signal from the external power supply voltage detecting means and / or the temperature detecting means by changing the power supply voltage to the internal circuit to thereby maintain the operating speed of the internal circuit to be constant.

An input buffer of the present invention has dual paths for increasing input signal processing speed by using two input buffers having input characteristics that differ from each other. The input buffer includes an input terminal receiving an external input signal; and first and second input buffers, both coupled to the input terminal for transferring an external input signal. The output signal of the second input buffer is blocked when the first input buffer transfers the external input signal, and the output signal of the first input buffer is blocked when the second input buffer transfers the external input signal.

A current mode logic digital circuit is provided comprising a logic circuit component having at least one data input node and at least one output node. A load is coupled between a power supply node and the output node. The load comprises a folded active inductor coupled to the output node.

A semiconductor integrated circuit is constructed with composite pass-transistor logic circuits serving as elementary circuit units each including a plurality of pass-transistor logic trees and a multiple-input logic gate. A wide variety of logical operations, even complex opearations, can be efficiently expressed using the composite pass-transistor logic circuit, and the resultant logic circuit can operate at a high speed. Thus, the semiconductor integrated circuit of the present invention can realize various logic functions required for various users in an efficient fashion. The present invention is particularly useful when applied to a field-programmable gate array integrated circuit, since complex logical operations can be expressed in a simple and efficient fashion by the composite pass-transistor logic circuits. The gate array integrated circuit obtained in accordance with the present invention can operate at a high speed with low power consumption. The present invention also discloses a basic cell suitable for use in an integrated circuit in the form of a gate array, and more particularly, a programmable logic block for use in a field programmable gate array integrated circuit.

A plurality of MOS transistors each having an SOI structure includes, in mixed form, those brought into body floating and whose body voltages are fixed and variably set. When a high-speed operation is expected in a logic circuit in which operating power is relatively a low voltage and a switching operation is principally performed, body floating may be adopted. Body voltage fixing may be adopted in an analog system circuit that essentially dislikes a kink phenomenon of a current-voltage characteristic. Body bias variable control may be adopted in a logic circuit that requires the speedup of operation in an active state and needs low power consumption in a standby state. Providing in mixed form the transistors which are subjected to the body floating and the body voltage fixing and which are variably controlled in body voltage, makes it easier to adopt an accurate body bias according to a circuit function and a circuit configuration in terms of the speedup of operation and the low power consumption.

A level shifter including a first boost circuit, an inverter, a second boost circuit and a level shift circuit is disclosed. The first boost circuit receives an input signal, and a first amplification factor for the input signal is determined based on a control signal. The inverter receives the input signal to generate an inverted input signal. The second boost circuit is coupled to an output terminal of the inverter to receive the inverted input signal, and a second amplification factor for the inverted input signal is determined based on the control signal. The level shift circuit has a first input terminal and a second input terminal respectively coupled to output terminals of the first boost circuit and second boost circuit to change the voltage level of output signals from the first boost circuit and second boost circuit to a first voltage level.

A level shifter is presented that allows fast switching while requiring low power. In accordance with some embodiments of the invention, the level shifter is a two stage level shifting circuit with p-channel and n-channel transistors biased so as to limit the potential between the source to gate or drain to gate of any of the transistors. Pull-up transistors are placed in a transition state so that spikes resulting from an increasing or decreasing input voltage turn on or off the pull up transistors to assist in the switching.

An AC current booster for high speed, high frequency applications having a single-ended output embodiment and a differential output embodiment. The embodiments of the present invention allow bifurcated control of the AC switching rate and the DC state of a given output signal, in order to achieve faster rising and falling edge rates without an undesirable increase in output voltage swing.

The invention simplifies the configuration of a level shifter and to allow fast operation. A level shifter includes a capacitor, to a first end of which a low-amplitude logic signal is input; first TFTs to apply an offset voltage to a second end of the capacitor; a capacitor, to a first end of which the low-amplitude logic signal is input; third TFTs to apply an offset voltage to a second end of the capacitor; and second TFTs connected in series between a supply line of a power supply voltage for a high-amplitude logic signal and a supply line of a reference voltage therefor, a node therebetween serving as an output terminal. A threshold voltage of one of the second TFTs is set to be not higher than the offset voltage applied by the first TFTs , and an offset voltage of the other of the second TFTs is set to be higher than or equal to the offset voltage applied by the third TFTs.

Apparatus and methods advantageously maintain transistors of open-drain differential pairs biased in the saturation region when “active,” rather in than the triode or linear region. The biasing techniques are effective over a broad range of process, voltage, and temperature (PVT) variations. By controlling a high voltage level used to drive the gate of a transistor of the differential pair, the biasing of the transistor in the saturation region is maintained. In one embodiment, the low voltage level used to cut off the transistor of the differential pair is also controlled. These techniques advantageously permit differential drivers to exhibit relatively large output swings, relatively high edge rates, relatively high return loss, and relatively good efficiency.