175results about How to "Increase delay time" patented technology

A mass spectrometer is disclosed wherein ions having a particular desired charge state are selected by operating an ion mobility spectrometer in combination with a quadrupole mass filter. Precursor ions are fragmented or reacted to form product ions in a collision cell ion trap and sent back upstream to an upstream ion trap. The fragment or product ions are then passed through the ion mobility spectrometer wherein they become temporally separated according to their ion mobility. Fragment or product ions are then re-trapped in the collision cell ion trap before being released therefrom in packets. A pusher electrode of a time of flight mass analyzer is energized a predetermined period of time after a packet of ions is released from the collision cell ion trap. Accordingly, it is possible to select multiply charged precursor ions from a background of singly charged ions, fragment them, and mass analyze the fragment ions with a near 100% duty cycle across the whole mass range.

A radio transmitter / receiver having a QoS control unit for outputting the transmission data in order taking the quality of service (QoS) into consideration. In the case where the information transmission rate for a radio section is not lower than a threshold value, the QoS control operation of the transmission data is omitted, and the transmission data are output in the order of input. In the case where the information transmission rate for the radio section is lower than the threshold value, on the other hand, the QoS control mode is switched in accordance with the information transmission rate for the radio section.

In a level shifter, in the case where the amplitude voltage of an input signal (i.e., a first power voltage VDDL) input to an input terminal is changed to be higher and the amplitude voltage of an output signal (i.e., a second power voltage VDDH) output from an output terminal is changed to be lower, a fall delay time of the signal output from the output terminal tends to be longer than a rise delay time of the signal. However, an inverted input signal obtained by an inverter is input to a level shifting unit and also to the gate of an N-type transistor, and therefore, the N-type transistor is turned on at the fall of the input signal input to the input terminal, so as to supply a current based on the second power voltage VDDH to an output node of the level shifting unit for assisting the shift into H level performed in the level shifting unit. Accordingly, even when at least one of the amplitude voltage of the input signal and the amplitude voltage of the output signal is changed, balance between the fall delay time characteristic and the rise delay time characteristic of the output signal can be satisfactorily kept.

A master-slave-type scanning flip-flop circuit is capable of operating at a higher speed by reducing a load capacity of a clock controller. The master-slave-type scanning flip-flop circuit is used to test a semiconductor integrated circuit device, and has a master latch and a slave latch each for temporarily holding an input signal, a first scan controller, a clock controller, and a second scan controller. The first scan controller receives an output signal from the master latch and outputs the received output signal in synchronism with a scan clock which is a clock for testing the semiconductor integrated circuit device, when the semiconductor integrated circuit device is tested. The clock controller receives an output signal from the first scan controller and outputs the received output signal to the slave unit in synchronism with a predetermined clock when in a normal mode of operation. The second scan controller has an input terminal connected to an output terminal of the first scan controller, and outputs a scan-out signal corresponding to a scan-in signal which is an input signal for testing the semiconductor integrated circuit device, in synchronism with the scan clock when the semiconductor integrated circuit device is tested.

In addition to two-stage CMOS inverters inverting and amplifying the input signal, a rising edge detector detects the rising edge of the input signal, and outputs a rising edge detection signal having a pulse width corresponding to ambient temperature, a PMOS drives the output node to the power supply potential according to the rising edge detection signal, a falling edge detector detects the falling edge of the input signal and outputs a falling edge detection signal having a pulse width corresponding to ambient temperature, and an NMOS drives the output node to ground potential according to the falling edge detection signal. When ambient temperature rises, and delay time of the inverters are thereby increased, pulse widths of the rising and falling edge detection signals are increased. The additional driving restrains delay time variation in a driving circuit due to ambient temperature change.

The invention relates to the field of multimedia data processing, and discloses a beautifying method and system for virtual scene live. The method comprising the steps that the data of a camera device are acquired in real time to acquire first image data; the first image data are converted into a texture image, and the texture image is updated to a virtual scene; a first object is extracted from the virtual scene through a GPU; and the first object is beautified and the virtual scene is rendered to acquire a render image. According to the technical scheme, the data of the camera device are converted into the texture image; the texture image is updated to the virtual scene; at the rendering stage of the virtual scene, the first object is extracted through the GPU; the first object is beautified to acquire the render image; rendering and beautifying are carried out in parallel; and the delay time of beautifying in virtual scene live is greatly reduced.

A mass spectrometer is disclosed wherein ions having a particular desired charge state are selected by operating an ion mobility spectrometer in combination with a quadrupole mass filter. Precursor ions are fragmented or reacted to form product ions in a collision cell ion trap and sent back upstream to an upstream ion trap. The fragment or product ions are then passed through the ion mobility spectrometer wherein they become temporally separated according to their ion mobility. Fragment or product ions are then re-trapped in the collision cell ion trap before being released therefrom in packets. A pusher electrode of a time of flight mass analyser is energised a predetermined period of time after a packet of ions is released from the collision cell ion trap. Accordingly, it is possible to select multiply charged precursor ions from a background of singly charged ions, fragment them, and mass analyse the fragment ions with a near 100% duty cycle across the whole mass range.

A regenerative relay method includes the steps of: i) calculating an error rate of a transmission path between the first half apparatus and a main apparatus; ii) calculating an error rate of a transmission path between the main apparatus and the latter apparatus; iii) adding the error rates; iv) selecting the error correction code and data before the error is corrected in the main apparatus so as to be supplied to the latter apparatus if the added error rates are lower than a designated error correction threshold; and v) selecting data after the error is corrected in the main apparatus and the other error correction code generated from the data so as to be supplied to the latter apparatus if the added error rates are higher than the designated error correction threshold.

The Objective of the present invention is to provide a delay unit for door with a door closer, which is capable of automatically closing the door after the elapse of a certain time since the door was opened and can be installed in case that the door closer is embedded inside the building and thereby being not exposed.The objective is solved by providing a delay unit 5 for door with a door closer comprising: a first sensor for detecting the door 2 opened to the first angle A, a lock unit 7 for electrically lock / unlock of the rotation of the rotation axis 3 of the door 2, a timer, a first sensor, and a control means, with which the first sensor, lock unit 7, and timer is connected, for controlling the lock unit 7 based on the signals from the first sensor and timer.

A picture encoding system conversion device and a code rate conversion device for realizing the conversion taking into account both time delay and picture quality using the information on the code volume of the encoding parameters, input and output buffers and an input bitstream. There are provided a decoder 1 including an input buffer 21, a VLD unit 22, an inverse quantizer 23, an IDCT unit 24, an adder 35, a frame memory 26 and a motion compensation prediction unit 27; an encoder 2 including an adder 31, a DCT unit 32, a quantizer 33, an inverse quantizer 34, an IDCT unit 35, an adder 36, a frame memory unit 37, a motion compensation prediction unit 38, a VLD unit 39 and an output buffer 40; and a transcoder controller 3 including a decoder monitor unit 51, an input buffer monitor unit 52, a reception transmission channel monitor 53, a sending transmission channel monitor 63, an output buffer monitor unit 62 and a quantization step controller 74. The quantization step controller 74 modifies the quantization step of the encoder based on the information from the input buffer monitor, output buffer monitor, decoder monitor, reception transmission channel monitor and sending transmission channel monitor.

In a level shifter, in the case where the amplitude voltage of an input signal (i.e., a first power voltage VDDL) input to an input terminal is changed to be higher and the amplitude voltage of an output signal (i.e., a second power voltage VDDH) output from an output terminal is changed to be lower, a fall delay time of the signal output from the output terminal tends to be longer than a rise delay time of the signal. However, an inverted input signal obtained by an inverter is input to a level shifting unit and also to the gate of an N-type transistor, and therefore, the N-type transistor is turned on at the fall of the input signal input to the input terminal, so as to supply a current based on the second power voltage VDDH to an output node of the level shifting unit for assisting the shift into H level performed in the level shifting unit. Accordingly, even when at least one of the amplitude voltage of the input signal and the amplitude voltage of the output signal is changed, balance between the fall delay time characteristic and the rise delay time characteristic of the output signal can be satisfactorily kept.

An invention is disclosed for determining integrated circuit (IC) logic speed. A storage element is provided that includes a reset input in electrical communication with a reset pin. A reset signal is then asserted at the reset pin, and a reset time is measured. The reset time is defined as the time period beginning when the reset signal is asserted and ending when the storage element resets. In this manner, the reset time can be used to determine a speed of the IC logic relative to a process. In one aspect, delay logic is provided that is in electrical communication with the reset pin and in electrical communication with the storage element. In this aspect, the delay logic delays the reset signal for a predetermined time period. Optionally, the reset time can be compared to a predetermined fast corner reset time and a predetermined slow corner reset time. Further, the IC logic speed can be correlated to a simulation using the embodiments of the present invention.

An apparatus includes a sample holding circuit, a comparator, a digital-to-analog converter, a clock generator, a successive approximation logic circuit, and a background calibration circuit. The apparatus converts an analog signal into digital data based on an asynchronous clock signal. The clock signal follows the number of clocks in a converting operation section through a background calibration scheme.

A data output driver and a semiconductor memory device having the same are disclosed. This data output driver includes: a rising transition slope adjuster including a plurality of first delay units cascade-connected to each other and receiving data and generating delayed data, each of the first delay units having a delay time which varies in response to a first control signal; a falling transition slope adjuster including a plurality of second delay units cascade-connected to each other and receiving inverted data and generating delayed inverted data, each of the second delay units having a delay time which varies in response to a second control signal; a pull-up driver including a plurality of pull-up circuits, the driving capabilities of the pull-up circuits being adjustable in response to a third control signal, each pull-up circuit pulling-up output data in response to each of the data and the delayed data; and a pull-down driver including a plurality of pull-down circuits, the driving capabilities of the pull-down circuits being adjustable in response to a fourth control signal, each pull-down circuit pulling-down output data in response to each of the inverted data and the delayed inverted data, wherein the first control signal varies in response to the third control signal, and wherein the second control signal varies in response to the fourth control signal. Accordingly, the rising and falling transition slopes of the output data can be constant even when the driving capability is varied, so that output data having desired characteristics can be produced.

An embodiment of the invention provides a storage card base, a mobile terminal and a method for protecting a storage card. The storage card base comprises a first contact point, a second contact point, a guide groove, and a junction embedded guide groove. The first contact point is disposed on a foundation of the storage card base. The second contact point is disposed on the foundation of the storage card base and is electrically connected with the first contact point when an upper cover of the storage card base is closed. The guide groove is disposed on the foundation of the storage card base and is located on a side of a junction which connects the foundation and the upper cover. The storage card base enables increase of delay time of stopping read-write protection. The storage card is protected timely, and repair rate of the storage card is reduced.