635results about How to "Improve read and write speed" patented technology

A memory storage and retrieval device containing (a) an electrically conductive first electrode; (b) an electrically conductive second electrode; (c) a layer stack intermediate the first and second electrodes containing (d) at least one active layer with variable electrical conductivity; and (e) at least one passive layer containing a source material for varying the electrical conductivity of the at least one active layer upon application of an electrical potential difference between the first and second electrodes.

A memory including memory cells having active and passive layers may store multiple information bits. The active layer may include an organic polymer that has a variable resistance based on the movement of charged species (ions or ions and electrons) between the passive layer and the active layer. The passive layer may be a super-ionic material that has high ion and electron mobility. The active layer may be self-assembled from a monomer in a liquid or gas.

The invention discloses a NAND Flash memory optimization management method based on a data exchange zone, which comprises the following steps: at least 2 blocks are set on the NAND Flash as the data exchange zone; a dynamic data effectiveness identification item is added for recording the aging degree of the data blocks in the data exchange zone; and the data block, before being modified during the setting period, is written into the real physical address of the flash memory after a logical address is re-mapped. By the management method, through the data exchange zone of a plurality of blocks set in the NAND Flash chip by a flash memory controller, the mid-process data during the read-write is stored by buffering, thus reducing the write-in frequency in the system document zone of the NAND Flash chip, increasing the read-write speed of the chip, as well as balancing the abrasion of the chip and prolonging the service life of the NAND Flash.

The invention discloses a multichannel flash memory transmission controller and chip with the controller and storage equipment, which comprises the following parts: main control state set, bus control unit and data bus control unit, wherein the bus control unit sends control signal to several flash memories through a group of multiplying control bus, which returns the state signal to main control state set; the state signal of several flash memories is input in the bus control unit at line pattern through multiplying control bus; several groups of individual data bus transmits data to the data bus control unit simultaneously. The invention improves the reading and writing speed of flash memory greatly.

The invention discloses a preprocessing method of multi-source heterogeneous big data, comprising the following steps: 1, heterogeneous data storage: extracting data from heterogeneous data sources according to preset conditions and uploading the data to a distributed file system HDFS for storage; 2, data cleaning: loading the data in the distributed file system HDFS into the memory through a Spark frame, removing the duplicate data and noise data, and transforming the format; 3, entity identification: identifying different representations of the same entity for the cleaned data, correctly identifying all the different entities, and merging the data of the same entity; 4, removal of redundancy: using hash-based duplicate data removal technology to remove redundant data. The method of the invention can reduce the storage resource and the network bandwidth, improve the data storage efficiency, and improve the quality of the subsequent data analysis work.

The embodiment of the invention discloses a method, a system and an apparatus for providing ordered contents, wherein the method for providing ordered contents comprises: calculating the heat of ordered contents and saving the request contents into a flash disk according to the calculated heat, so when a media server receives the ordering request, priority will be given to the ordered content saved in the flash disk. Through saving the hot movies into the flash disk inside the stream media server, the execution example of the invention can increase I / O read / write speed, and therefore improve the performance of unit stream media servers. Moreover, the flash disk is characterized in that no data are lost in power-off status; therefore, it is not necessary to read data of hot movies from hard drives into the flash disk even in a restart process, so as to improve the start-up speed.

An information sensing and storing device has a dual-MTJ (Magnetic Tunnel Junction) structure, and comprises a bottom electrode, an MTJ 1, a non-ferromagnetic metal isolation layer, an MTJ 2 and a top electrode sequentially from bottom to top, wherein a metal wire is arranged at one side of the device. A fabrication method of the information sensing and storing device comprises the five steps of: 1, depositing a magnetic multi-layer film material on a substrate; 2, performing annealing through an ultrahigh magnetic field vacuum annealing apparatus to fix the magnetization direction of a reference layer; 3, finishing shape fabrication of the dual-MTJ structure by using traditional nanometer device processing technologies such as photoetching, etching and magnetron sputtering; 4, depositing an isolation layer at the outer side of the dual-MTJ structure, and configuring the metal wire near the dual-MTJ structure through the technologies such as photoetching, etching and inlaying; and 5, forming a metal electrode at the top of the dual-MTJ structure by using the processing technologies such as photoetching, etching and inlaying for subsequent integration or test.

The invention provides a method and a device for increasing the read-write rate of a double data rate synchronous dynamic random access memory (DDRSDRAM). The method comprises the following steps of: receiving a read address corresponding to a read request of a packet; caching the read address in a corresponding first first-in first-out queue (FIFO) according to a bank number; reading the read address out from a first FIFO in the first FIFO for the first time; if the next read address in the first FIFO and the read address read out for the first time belong to same-line addresses, continuously reading the first FIFO; and if the next read address in the first FIFO and the read address read out for the first time belong to different-line addresses, reading the next first FIFO in a polling mode. By the method and the device for increasing the read-write rate of the DDRSDRAM, realization difficulties are reduced, the realizability and the adjustment force of a field programmable gate array (FPGA) project are improved, and the read-write efficiency of the DDRSDRAM is greatly improved by limited resources.

The invention discloses a dirty data write-back system in a virtual environment. The dirty data write-back system comprises a virtual machine module, a privileged operation module and a virtual machine manager module, wherein the virtual machine module is used for sending a physical disk read-write request and dirty data from a user application program to the privileged operation module; and the privileged operation module is used for storing the physical disk read-write request and the dirty data in a virtual machine cache of the virtual machine manager module, and processing the physical disk read-write request when the utilization rate of the virtual machine cache reaches a predefined threshold value, and transmitting the dirty data to a physical disk. According to the dirty data write-back system disclosed by the invention, the read-write speed of the physical disk in the virtual machine and the utilization rate of the bandwidth of the physical disk in the virtual machine can be increased, the reliability of a file system in the virtual machine can be enhanced, the interferences of read-write operations of the physical disks among different virtual machines on the same physical platform can be reduced, and the transparency on application programs in the virtual machine and an operating system in the virtual machine and the expandability on a virtual platform are realized.

The invention relates to a data acquisition and emulation system suitable for an underlying protocol stack of a digital communication terminal. The system comprises a digital signal processor (DSP), a data acquisition system, and a computer emulation system, wherein the data acquisition system comprises a field-programmable gate array (FPGA), a universal serial bus (USB) interface chip, and a memory corresponding to the FPGA and the USB interface chip; the computer emulation system comprises a computer, and a data receiving program module and a system emulation program module operated on the computer; the DSP is connected to the FPGA through an address bus, a data bus, a chip selection, and a write enable respectively; and the acquisition output end of the FPGA is connected to the data input end of the USB interface chip; and the USB interface chip is connected to the computer through a USB bus. The data acquisition and emulation system has the advantages that: the acquired data and the data input by the underlying protocol stack can be ensured to be completely consistent by directly connecting the data acquisition system with the DSP high-speed data bus; the data bus has high read and write rate and low time consumption, so that the operation of the underlying protocol stack cannot be affected; the system is suitable for the development and debugging of the underlying protocol stack so as to track and find out problems and search program defects.