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FIFO burst buffer with large capacity based on SDRAM and data storage method

A technology of data storage and buffer, applied in the field of burst buffer, which can solve the problems of small FIFO burst buffer capacity, inability to complete read and write operations at the same time, and high price

Inactive Publication Date: 2008-11-19
HARBIN INST OF TECH
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

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Problems solved by technology

[0008] In order to solve the problem of small FIFO burst buffer capacity and high price, and the disadvantages of inability to complete read and write operations and low operation efficiency caused by adopting SDRAM memory, the present invention proposes a large-capacity FIFO burst buffer based on SDRAM. Buffer and data storage method

Method used

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  • FIFO burst buffer with large capacity based on SDRAM and data storage method
  • FIFO burst buffer with large capacity based on SDRAM and data storage method
  • FIFO burst buffer with large capacity based on SDRAM and data storage method

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specific Embodiment approach 1

[0025] Specific implementation mode one: combine figure 1 Describe this embodiment mode, it is based on the large-capacity FIFO burst register master controller 1 of SDRAM, SDRAM controller 2, input buffer 3 and output buffer 4 to form; The data input end of input buffer 3 is the external data input end , the read control end of the input buffer 3 is connected to the input buffer control end of the main controller 1, and the SDRAM memory data output end of the input buffer 3 is connected to the data input end of the SDRAM controller 2; the data input end of the input buffer 3 is directly output Connect the data direct input end of the output buffer 4; the write control end of the output buffer 4 is connected to the output buffer control end of the main controller 1, and the SDRAM memory data input end of the output buffer 4 is connected to the data output end of the SDRAM controller 2 , the data output end of the output buffer 4 is an external data output end; the SDRAM read-...

specific Embodiment approach 2

[0026] Embodiment 2: This embodiment differs from Embodiment 1 in that the input buffer 3 and the output buffer 4 are two small-capacity FIFO memories. Other compositions and connection methods are the same as those in Embodiment 1.

specific Embodiment approach 3

[0027] Specific implementation mode three: combination figure 2 Describe this embodiment, the difference between this embodiment and specific embodiment one is that the whole system of this embodiment is implemented in FPGA, and the input buffer 3 and output buffer 4 used as data buffering all use the small-capacity FIFO module inside FPGA Realize, SDRAM controller 2 adopts the SDRAM memory inside FPGA, the SDRAM memory of DDR or DDRII series;

[0028] This implementation mode adopts the VHDL language to be written and applied on the Quartus II software. Before applying this system, the SDRAM to be used must be determined. According to the selected SDRAM data sheet, some important parameters, the bit width DSIZE of the data, and each BANK address row number ROWSIZE and column number COLSIZE, BANK number BANKSIZE, core clock rate clk_core, refresh command duration t RFC , precharge effective time tRP , the time interval t between column read and write commands and row effecti...

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Abstract

A FIFO burst buffer memory with large capacity based on SDRAM and a data storage method are disclosed, relating to burst buffer memory, solving the problems of small capacity and high cost on FIFO burst buffer memories and avoiding the defect on SDRAM storages that reading and writing operations can not be done at the same time and the defect of low operation efficiency. The SDRAM controller of the invention is a module used to control the SDRAM storage; the master controller is the control center of the whole system, with the responsibility for attempering the whole system; the input buffer memory and the output buffer memory, two FIFOs with small capacity, are respectively used as cushions for input date and output data; the input data first enter the input buffer memory and when the data in the input buffer memory are added up to certain number, the master controller transmits part of the data in the input buffer memory to the SDRAM storage. When the output buffer memory is in deficiency of data, the master controller transmits part of the data in the SDRAM storage to the output buffer memory. The FIFO burst buffer memory is low in cost and has a data read-write speed of 75MHz.

Description

technical field [0001] The invention relates to the field of burst buffering. Background technique [0002] The burst buffer is mainly used for data transmission between different clock domains or interfaces with different data widths, that is, the rates of input data and output data are different or the data widths of input data and output data are different. There are currently three main caches. [0003] The first type of dual-port SRAM has a speed of up to hundreds of megabytes, can read and write at the same time, and has an address line to control the access position. Its disadvantage is that the capacity is small, generally less than 1MB, which cannot meet the storage requirements of large capacity. , the price is also high. [0004] The second type is "ping-pong" SDRAM. The so-called "ping-pong" refers to using two SDRAMs, one for reading and one for writing, so that read and write operations can be performed at the same time. The read and write speed can reach 166...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): G11C7/10G06F5/10
Inventor 任广辉李宝王刚毅
Owner HARBIN INST OF TECH
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