Looking for breakthrough ideas for innovation challenges? Try Patsnap Eureka!

AXI bus based convenient configurable frame data access control system

An access control and bus control technology, which is applied in electrical digital data processing, instruments, etc., can solve the problems of complex operation and low overall system performance, and achieves the improvement of data transmission rate, simplification of multiple handshake operations, and convenient access methods. Effect

Active Publication Date: 2016-04-06
HARBIN INST OF TECH
View PDF3 Cites 29 Cited by
  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

[0004] The present invention aims to solve the problems of complex operation and low overall performance of the existing method, and provides a convenient and configurable frame data access control system based on the AXI bus

Method used

the structure of the environmentally friendly knitted fabric provided by the present invention; figure 2 Flow chart of the yarn wrapping machine for environmentally friendly knitted fabrics and storage devices; image 3 Is the parameter map of the yarn covering machine
View more

Image

Smart Image Click on the blue labels to locate them in the text.
Viewing Examples
Smart Image
  • AXI bus based convenient configurable frame data access control system
  • AXI bus based convenient configurable frame data access control system
  • AXI bus based convenient configurable frame data access control system

Examples

Experimental program
Comparison scheme
Effect test

specific Embodiment approach 1

[0032] Specific embodiment one: the configuration module of this embodiment, buffer module namely FIFO module, write address generator module, read address generator module, read state machine control module, write state machine control module and AXI bus control module;

[0033] Wherein, the configuration module is input by the user to configure the parameters of the write address generator module, the read address generator module and the AXI bus control module;

[0034] The parameters are:

[0035] The data bit width data_width is n, the address bit width addr_width is m, and the number of transmission rounds burst_length is l;

[0036] The data bit width n determines the data width transmitted by the AXI bus;

[0037] The address bit width m determines the storage depth of the memory as 2 m bits;

[0038] The configurable range of l is: 1, 2, 4, 8, 16, 32, 64, 128 and 256. This parameter indicates the number of data continuously transmitted without interval during each ...

specific Embodiment approach 2

[0050] Specific embodiment two: the difference between this embodiment and specific embodiment one is: described configuration module is connected with write address generator module, read address generator module and AXI bus control module, carries out read and write address and AXI bus transmission parameter configuration ;

[0051] The buffer module is connected with the write state machine control module and the read state machine control module, and buffers the read and write data and addresses;

[0052] The write state machine control module and the read state machine control module are connected with the AXI bus control module to realize the interaction of data, address and other handshake signals with the AXI bus;

[0053] The entire system access control system is connected with the external memory through the AXI bus to realize the high-speed data access buffer function.

[0054] Other steps and parameters are the same as those in Embodiment 1.

specific Embodiment approach 3

[0055] Specific implementation mode three: the difference between this implementation mode and specific implementation mode one or two is that: the reading sequence of the AXI bus burst transmission controlled by the read state machine control module is specifically:

[0056] The reading sequence of the read state machine control module controlling AXI bus burst transmission is specifically:

[0057] The read state machine control module starts the "read" state when it is not empty, writes the address in the read address buffer submodule to the AXI bus, and reads the data on the corresponding address in the memory to the read data buffer submodule Among them, the data transmission adopts the AXI bus burst transmission, that is, it does not need to take the address from the read address buffer submodule again, but uses the method of automatically adding 1 to the address to read l data at a time;

[0058] The read state machine control module contains two states: READ_IDLE and I...

the structure of the environmentally friendly knitted fabric provided by the present invention; figure 2 Flow chart of the yarn wrapping machine for environmentally friendly knitted fabrics and storage devices; image 3 Is the parameter map of the yarn covering machine
Login to View More

PUM

No PUM Login to View More

Abstract

The invention relates to an AXI bus based convenient configurable frame data access control system, aiming to solve problems that existing methods are complex to operate and the systems in the prior art have low overall performance. The system comprises a configuration module, a buffer module, a write address generator module, a read address generator module, a read state machine control module, a write state machine control module and an AXI bus control module. The buffer module comprises a write data buffer submodule, a write address buffer submodule, a read data buffer submodule, and a read address buffer submodule. The system is applied to the field of data access.

Description

technical field [0001] The invention relates to a convenient and configurable frame data access control system based on AXI bus. Background technique [0002] In data transmission and storage systems, a convenient and efficient off-chip memory access method can increase data transmission rate and greatly improve system performance. [0003] The traditional way of accessing data in the off-chip memory is performed by the memory controller. The memory controller is a bus circuit controller used to manage and plan the transmission from the processor to the memory. It converts the interface between the processor and the memory, and converts the read and write instructions issued by the processor into a certain time sequence. Regular signals to access memory. However, this traditional access method requires the necessary control of many signals involved in data access through the storage controller, including data signals, address signals and other command signals, which is ver...

Claims

the structure of the environmentally friendly knitted fabric provided by the present invention; figure 2 Flow chart of the yarn wrapping machine for environmentally friendly knitted fabrics and storage devices; image 3 Is the parameter map of the yarn covering machine
Login to View More

Application Information

Patent Timeline
no application Login to View More
Patent Type & Authority Applications(China)
IPC IPC(8): G06F13/16
CPCG06F13/1673G06F2213/16
Inventor 王少军马宁崔秀海刘大同刘瀚博姬耀
Owner HARBIN INST OF TECH
Who we serve
  • R&D Engineer
  • R&D Manager
  • IP Professional
Why Patsnap Eureka
  • Industry Leading Data Capabilities
  • Powerful AI technology
  • Patent DNA Extraction
Social media
Patsnap Eureka Blog
Learn More
PatSnap group products

Browse by: Latest US Patents, China's latest patents, Technical Efficacy Thesaurus, Application Domain, Technology Topic, Popular Technical Reports.

© 2024 PatSnap. All rights reserved.Legal|Privacy policy|Modern Slavery Act Transparency Statement|Sitemap|About US| Contact US: help@patsnap.com