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Static random memory unit

A static random access memory and inverter technology, applied in the semiconductor field, can solve the problems of reducing the read and write speed of SRAM cells and difficult to guarantee the stability of SRAM read and write, so as to improve the read and write stability, suppress the single-event flip, and prolong the delay. effect of time

Inactive Publication Date: 2013-01-30
SHANGHAI INTEGRATED CIRCUIT RES & DEV CENT
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  • Summary
  • Abstract
  • Description
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  • Application Information

AI Technical Summary

Problems solved by technology

[0005] Although the introduction of resistance or capacitance in the SRAM unit can effectively achieve the purpose of suppressing single event flipping, it is not difficult to find that adding resistance or capacitance between the two inverters will inevitably greatly reduce the read and write speed of the SRAM unit
Usually, in order to effectively suppress single event flipping, the feedback resistance introduced in the SRAM unit needs to reach the order of mega-ohms. This high-resistance element makes it difficult to guarantee the read and write stability of the SRAM.

Method used

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Embodiment Construction

[0020] In order to better understand the technical content of the present invention, the preferred specific embodiments are illustrated as follows.

[0021] Please refer to Figure 4 , which shows a schematic structural diagram of the SRAM unit according to an embodiment of the present invention.

[0022] The SRAM unit of the present invention includes a first inverter INV1, a second inverter INV2, NMOS transmission gate transistors N13, N24, feedback resistors R1, R2 and feedback transistors T1, T2. The first inverter includes an NMOS transistor N11 and a PMOS transistor P11, and the second inverter INV2 includes an NMOS transistor N22 and a PMOS transistor P22. The drains of the NMOS transistor N11 and the PMOS transistor P11 are connected together as the output terminal S1 of the first inverter INV1 . The feedback resistor R1 and the feedback transistor T1 are coupled in parallel to the output terminal S1 of the first inverter INV1 and the input terminal of the second inv...

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Abstract

The invention discloses a static random memory unit, comprising a first inverter, a second inverter, a first feedback resistor, a second feedback resistor, a first feedback transistor and a second feedback transistor. The first feedback resistor and the first feedback transistor are in parallel connection and coupled to an output terminal of the first inverter and an input terminal of the second inverter; and the second feedback resistor and the second feedback transistor are in parallel connection and coupled to an input terminal of the first inverter and an output terminal of the second inverter. The invention can effectively improve single event upset resistance of the static random memory, and further ensure that the static random memory unit has high reading and writing speed in the states of reading and writing.

Description

technical field [0001] The invention relates to the technical field of semiconductors, in particular to a static random storage unit resistant to single event reversal effect. Background technique [0002] Static random access memory unit (SRAM unit) is the most commonly used semiconductor memory, which has the advantages of high speed and low power consumption. At present, the most common SRAM unit structure in the industry is six-tube SRAM, such as figure 1 As shown, it consists of 6 transistors. The PMOS transistor P11 and the NMOS transistor N11 constitute the first inverter INV1, and the PMOS transistor P22 and the NMOS transistor N22 constitute the second inverter INV2. Two inverters are cross-locked, that is, the output terminal S1 of the first inverter INV1 and the input terminal of the second inverter INV2 (that is, the gates of the PMOS transistor P22 and the NMOS transistor N22 ), and the output terminal S2 of INV2 is connected with the input terminal Q of INV...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): G11C11/413
Inventor 郭奥
Owner SHANGHAI INTEGRATED CIRCUIT RES & DEV CENT
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