A multi-core
digital signal processor is disclosed having a shared program memory with conditional
write protection. In one embodiment, the
digital signal processor includes a shared program memory, an emulation
logic module, and multiple processor cores each coupled to the shared program memory by corresponding instruction buses. The emulation
logic module preferably determines the operating
modes of each of the processors, e.g., whether they are operating in a
normal mode or an emulation mode. In the emulation mode, the emulation logic can alter the states of various processor hardware and the contents of various registers and memory. The instruction buses each include a read / write
signal that, while their corresponding processor cores are in
normal mode, is maintained in a read state. On the other hand, when the processor cores are in the emulation mode, the processor cores are allowed to determine the state of the instruction
bus read / write signals. Each instruction
bus read / write
signal is preferably generated by a
logic gate that prevents the processor core from affecting the read / write
signal value in
normal mode, but allows the processor core to determine the read / write signal value in emulation mode. In this manner, the
logic gate prevents write operations to the shared program memory when the emulation logic de-asserts a signal indicative of emulation mode, and allows write operations to the shared program memory when the emulation logic asserts the signal indicative of emulation mode. The
logic gate is preferably included in a
bus interface module in each processor core.