Dynamic semiconductor memory and semiconductor IC device

Abstract

A DRAM, including a plurality of banks each having a plurality of sub-arrays, and sense amplifier circuits commonly shared by sub-arrays in different banks, has a row access mode for activating a sub-array selected from each bank for reading or writing data, and a refresh mode for activating a plurality of sub-arrays in each bank and refreshing memory cell data therein at substantially the same timing. Sub-arrays in each bank activated at substantially the same timing in the refresh mode are more than sub-arrays in each bank activated in the row access model. Thereby, occurrence of operation constrains is minimized to ensure high-speed operation and improve the system performance of DRAMs employing the non-independent bank system.

Description

technical field [0001] The present invention relates to a dynamic semiconductor memory device (DRAM) and a semiconductor integrated circuit device, and in particular, to an improvement in refresh operation. Background technique [0002] In DRAM, the data of the storage unit must be refreshed, and the data of the entire unit needs to be refreshed within a certain period of time. If the refresh fails, it is impossible to read the data due to the leakage of the storage cell charge. [0003] Recently, as the capacity of DRAM increases, the time required for refreshing becomes longer, and the influence on the performance of the DRAM system must be taken into consideration. That is, the refresh operation of a DRAM is usually controlled by a memory controller, etc., and the time for the memory controller to output a refresh command increases as the capacity increases. This is because the normal operation time is compressed. [0004] As a method of solving this problem, there is a...

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Problems solved by technology

[0009] The above restrictive actions have an impact on the performance of the DRAM system

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