Latch circuit and semiconductor memory device

Abstract

latch circuits and semiconductor memory devices. The latch circuit includes an input circuit including an input PMOS transistor that causes a signal current corresponding to the sensed voltage to flow; a first inverter including a first PMOS transistor, a first NMOS transistor, and a first node. The first PMOS transistor and the first NMOS transistor are connected and connected to the input circuit; and the second inverter includes a second PMOS transistor, a second NMOS transistor and a second node, the second node connects the second PMOS transistor and the second NMOS transistor. The first inverter and the second inverter are connected in cascade.

Description

technical field [0001] The present invention relates to a latch circuit for temporarily storing, for example, data read from the semiconductor memory device, and a semiconductor memory device including the latch circuit. The semiconductor memory device is an electrically rewritable nonvolatile semiconductor memory device (Electrically Erasable Programmable Read Only Memory, EEPROM) such as a flash memory (flash memory). Background technique [0002] There is known a kind of NOR (NOR) type nonvolatile semiconductor memory device (especially NOR type flash EEPROM), and it is connected in parallel between bit line (bit line) and source electrode line (source line) and multiple Each word line (word line) corresponds to a plurality of memory cell transistors (memory cell transistors) (hereinafter referred to as memory cells) to form a memory cell array (memory cell array) to achieve high integration. [0003] figure 1 It is a block diagram showing the overall structure of a con...

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Problems solved by technology

[0038] However, for example, in Patent Document 1 to Patent Document 3, although various conventional latch circuits are disclosed, there is a problem that the current consumption is relatively large, the circuit size is also large, and high-speed operation cannot be realized.

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