Level chagning circuit

A technology for converting circuits and levels, which is applied in the direction of logic circuit connection/interface layout, electrical components, electronic switches, etc., and can solve problems such as area increase

Inactive Publication Date: 2004-05-26
CETUS TECH INC
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

However, in this method, there are still problems that the area increases due to the increase in the number of elements, and when the current supply circuit is constructed using transistors, there are still problems that a subthreshold current always flows.

Method used

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Examples

Experimental program
Comparison scheme
Effect test

Embodiment 1

[0060] figure 1 A schematic diagram showing a level conversion circuit according to Embodiment 1 of the present invention. exist figure 1 Here, a gate voltage control circuit 100 as a first gate voltage control circuit is connected to an output terminal VO as a second terminal, and has an output terminal 101 . A gate voltage control circuit 102 as a second gate voltage control circuit is connected to an output terminal VON as a first terminal, and has an output terminal 103 . The output terminal VO is a terminal for outputting a level-shifted signal in phase with the input signal VIN as the first input signal, and the output terminal VON is a terminal for outputting a level-shifted signal of the second input signal. The second input signal is inverted from the input signal VIN.

[0061] The voltage of the power supply 900 is the voltage level V1 as the first power supply voltage, the voltage of the power supply 901 is the voltage level V2 as the second power supply voltag...

Embodiment 2

[0075] Figure 3A Shown is a level conversion circuit diagram related to Embodiment 2 of the present invention. exist Figure 3A Among them, the gate voltage control circuit 100 is connected to the output terminal VO and has an output terminal 101 . The gate voltage control circuit 102 is connected to the output terminal VON and has an output terminal 103 . In the transistor 200 , the source is connected to the output terminal VO, and the gate and drain are connected in common to the output terminal 101 . The transistor 201 receives an inverted signal 908 of the input signal VIN to its gate, and its drain is connected to the drain of the transistor 200 . In the transistor 202 , its source is connected to the output terminal VON, and its gate and drain are commonly connected to the output terminal 103 . The gate of the transistor 203 receives the input signal VIN, and its drain is connected to the drain of the transistor 202 . The second conductivity type transistor 300 (h...

Embodiment 3

[0088] Figure 4A Shown is a level conversion circuit diagram related to Embodiment 3 of the present invention.

[0089] exist Figure 4A Among them, the gate voltage control circuit 100 is connected to the output terminal VO and has an output terminal 101 . The gate voltage control circuit 102 is connected to the output terminal VON and has an output terminal 103 . The second conductivity type depletion transistor 400 (hereinafter referred to as the transistor 400) of the eleventh transistor has its source connected to the output terminal VO, and its gate and drain connected in common, so that the voltage between the gate and the source is 0V. drain current flows. The transistor 201 receives an inverted signal of the input signal VIN to its gate, and its drain is connected to the drain of the transistor 400 . The second conduction type depletion-type transistor 401 (hereinafter referred to as transistor 401) of the twelfth transistor has its source connected to the output...

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PUM

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Abstract

A level shift circuit which realizes a high-speed and power-saved operation particularly when the input voltage is at a low level is provided. The level shift circuit of the present invention comprises a first gate voltage control circuit controlled by a inverted signal of an input signal, which is inserted between a gate of a third transistor and a second output terminal; a second gate voltage control circuit controlled by the input signal, which is inserted between a gate of a fourth transistor and a first output terminal; a first transistor; and a second transistor. When the input signal shifts from 'H' to 'L', the first transistor turns OFF, the third transistor is turned ON by the first gate voltage control circuit, and then a voltage of the first output terminal rises. The second transistor turns ON, the fourth transistor is turned OFF by the second gate voltage control circuit, and then the voltage of the second output terminal goes down.

Description

technical field [0001] The invention relates to a level conversion circuit, in particular to a level conversion circuit suitable for high speed and low power consumption when converting an input signal of a low voltage level into a high voltage level. Background technique [0002] Figure 14A Represents a prior art level shifting circuit. exist Figure 14A Among them, the terminal V0 outputs a signal in phase with the input signal VIN, and the terminal VON outputs a signal in phase with the input signal VIN. [0003] The voltage level of the first power supply 1000 (hereinafter referred to as power supply 1000) is V1, the voltage level of the second power supply 1001 (hereinafter referred to as power supply 1001) is V2, and the voltage level of the third power supply 1002 (hereinafter referred to as power supply 1002) is V1. Flat for V3. The voltage level V3 is the voltage amplitude of the input signal VIN, and the voltage V3 and the voltage V2 are at the same voltage leve...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): H03K17/16H03K3/356H03K17/10H03K17/687H03K19/0185H03L5/00
CPCH03K17/102H03K3/356113
Inventor 山平征二服部规男荒川健
Owner CETUS TECH INC
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