Semiconductor memory device

Abstract

A memory to which a bit line potential step-down technique is applied is provided. The memory includes an IO block including first transistors which control potentials of first bit lines provided with respect to columns of memory cells, and first logic gates which control the first transistors. The drain or source of each first transistor is connected to an input of the corresponding first logic gate, and the gate of each first transistor is connected to an output of the corresponding first logic gate. The first transistors are driven by pulses.

Description

technical field [0001] The present invention relates to a semiconductor memory device, in particular to a technology for controlling the potential of a bit line of a memory circuit. Background technique [0002] Conventionally, in order to improve the SNM (Static Noise Margin) of the memory cell of the SRAM (Static Random Access Memory), there is known a method in which an N-channel MOS (NMOS) transistor connected to a bit line is pulse-driven to lower the voltage of the bit line. technology. Among them, as a data reading method, a sense amplifier that detects a slight potential difference between a pair of bit lines is used (see Non-Patent Document 1). [0003] On the other hand, there is also known a technique for controlling the potential level of a signal line by using a decoding circuit unit for driving a word line of a semiconductor memory device (see Patent Document 1). [0004] Patent Document 1: Japanese Patent Laid-Open No. 2007-164922 [0005] Non-Patent Docume...

AI Technical Summary

Problems solved by technology

However, when the power supply voltage is Vdd and the threshold voltage of the NMOS transistor is Vtn, a long precharge time is required to raise the potential of the signal line to Vdd-Vtn through the NMOS transistor.

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