31 results about "Threshold voltage degradation" patented technology

There are provided a substrate including an oxide TFT having improved initial threshold voltage degradation characteristics included in a driving circuit of a liquid crystal display (LCD) device, a method for fabricating the same, and a driving circuit for an LCD device using the same. The substrate including an oxide thin film transistor (TFT) includes: a base substrate divided into a pixel region and a driving circuit region; and a plurality of TFTs formed on the base substrate, wherein an initial threshold voltage of at least one of the plurality of TFTs formed in the driving circuit region is positive-shifted to have a predetermined level.

It is an object of the present invention to provide a device which can be easily manufactured and obtain a ground state of an arbitrary Ising model. A semiconductor device includes a first memory cell and a second memory cell that interacts with the first memory cell, in which storage content of the first memory cell and the second memory cell is stochastically inverted. The storage content is stochastically inverted by dropping threshold voltages of the first memory cell and the second memory cell. The threshold voltages of the first and second memory cells are dropping by controlling substrate biases, power voltages, or trip points of the first and second memory cells.

A GaN power switching device comprises a GaN transistor switch SW_MAIN has an integrated drain voltage sense circuit, which comprises GaN sense transistor SW_SEN and GaN sense resistor RSEN, which at turn-on form a resistive divider for sensing the drain voltage of SW_MAIN to provide a drain voltage sense output VDSEN. Fault detection logic circuitry of a driver circuit generates a fault signal FLT when VDSEN reaches or exceeds a reference voltage Vref, which triggers fast turn-off of the gate of SW_MAIN, e.g. within less than 100 ns of an overcurrent or short circuit condition. During turn-off, RSEN resets VDSEN to zero. For two stage turn-off, the driver circuit further comprises fast soft turn-off circuitry which is triggered first by the fault signal to pull-down the gate voltage to the threshold voltage, followed by a delay before full turn-off of the gate of SW_MAIN by the gate driver.

The invention relates to the technical field of integrated circuits and provides a threshold voltage degradation measuring circuit. The circuit comprises two MOS (Metal Oxide Semiconductor) tubes which are connected in series, wherein the first MOS tube is a detected tube; a grid electrode of the first MOS tube is connected with first direct-current voltage, a source electrode and a substrate of the first MOS tube are simultaneously connected with source electrode voltage, and a drain electrode of the first MOS tube is connected with an output end; a grid electrode and a drain electrode of the second MOS tube are simultaneously connected with second direct-current voltage, and a source electrode and a substrate of the second MOS tube are simultaneously connected with the output end. According to the scheme disclosed by the invention, the threshold voltage degradation measuring circuit with a simple structure is provided; the circuit only comprises the two MOS tubes which are connected in series and the threshold voltage degradation condition of the tube to be detected can be directly measured by only measuring the voltage change of the output end; and the circuit only relates to the obtaining of one physical amount and does not need to carry out secondary process and analysis, so that the technical scheme has the advantages of simple structure, convenience for operation, time-saving property, accurate and direct results and easiness in implementation.

The invention provides a method for forming an NMOS (N-channel Metal Oxide Semiconductor) transistor. The method comprises the following steps of: providing a substrate and a grid structure located on the substrate; taking the grid structure as a mask to carry out ion implantation on the substrate, and forming a source area and a drain area in the substrate at the both sides of the grid structure; forming a stopping layer on the exposed surfaces of the substrate and the grid structure; forming a stress layer on the stopping layer, wherein the stopping layer is used for preventing hydrogen elements used in the forming environment of the stress layer from entering the source area and the drain area; carrying out heat treatment on the source area and the drain area; and removing the stopping layer and the strain layer. According to the method disclosed by the invention, the compact stopping layer is formed on the surfaces of the substrate and the grid structure before the stress layer is formed, so as to prevent the hydrogen elements used in the forming environment of the stress layer from entering the source area / drain area in the substrate. Therefore, the problem of descending of threshold voltage, caused when the diffusion of doped ions in the source area / drain area is enhanced by the hydrogen elements, is solved, the reliability of the threshold voltage is improved, and the property reliability of the NMOS transistor is further improved.

The invention discloses a method for recovering the threshold voltage reduction of a MOSFET after irradiation. The method comprises the following steps: step 1, providing the MOSFET, wherein the MOSFET is irradiated; and step 2: applying a voltage of a certain value to the gate or the drain of the MOSFET for a period of time so that a part of electrons enter the oxide layer of the gate of the MOSFET and are recombined with the trapped holes. The voltage is applied to the gate or the drain of the irradiated MOSFET so that the electrons enter the oxide layer of the gate and are recombined with trapped holes, the threshold voltage of the device can be recovered and the problem of severe threshold voltage reduction of the MOSFET at high temperature can be alleviated.

The invention discloses a manufacturing method of an NROM and a device thereof. The method comprises the following steps of: forming a source electrode and a drain electrode below a working surface of a semiconductor substrate; etching a chute on the semiconductor substrate between the source electrode and the drain electrode, and infusing silicon ion on the chute section of the semiconductor substrate so as to ensure non-crystallization of the semiconductor substrate on the surface of the chute; forming an ONO insulation layer on the surfaces of the semiconductor substrate, the source electrode and the drain electrode, wherein the ONO insulation layer is projected corresponding to the section of the chute and is inlayed in the chute of the semiconductor substrate; and forming a control grid on the surface of the ONO insulation layer between the source electrode and the drain electrode. Compared with the NROM device with reduced size in equal proportion, the NROM device during operation relatively lengthens the effective chute and solves all kinds of problems resulting from reducing the length of the chute, such as declination of the threshold voltage of the device, higher leakage current and interference generated between two locations.

The present invention provides a method of forming a semiconductor device. The method comprises the steps of: providing a substrate having a fin thereon; forming a dummy gate oxide layer at the side wall and the top portion of the fin; forming a protection layer on the dummy gate oxide layer; forming an isolation layer on the substrate, wherein the isolation layer is located on the protection layer and covers the side wall of the fin; performing ion doping for the fin after the isolation layer is formed; and removing the part of the isolation layer to form an isolation structure covering partof the side wall of the fin, wherein the isolation structure exposes part of the protection layer. The method of forming a semiconductor device forms the dummy gate oxide layer prior to ion doping toavoid the thermal effect in the process of forming the dummy gate oxide layer through thermal treatment, the thermal effect can allow the doped ions doped in the fin to be diffused, the diffusion of the doped ions can reduce the ion doping dosage in the fin to cause the threshold voltage drop and influence the device performance.

The invention discloses a method for manufacturing a MOS field effect transistor. In the double gate oxide etching step, only the medium-voltage thick gate oxide in the middle part of the silicon region of the low-voltage MOS tube is etched away, and the two ends in the width direction of the MOS tube are kept close to the From somewhere within the silicon region at the junction of the shallow trench isolation region and the silicon region to a medium voltage thick gate oxide at the junction of the shallow trench isolation region and the silicon region. The invention improves the threshold voltage of the total transistor of the low-voltage MOS field effect transistor by retaining the medium-voltage thick gate oxide at the edge of the silicon region of the low-voltage MOS transistor, and improves the problem of threshold voltage drop caused by the reverse narrow channel effect of the MOS field effect transistor.

The invention discloses an NBTI degradation model obtaining method based on nonuniform distribution interface traps. The method comprises the steps that 1, interface trap distributions in different zone of an MOS device are divided to obtain total distribution frame of the interface traps; 2, according to geometric construction, the interface trap distribution density in each zone is calculated, and the total density of the nonuniform distribution interface traps is obtained; 3, threshold voltage deviation caused by NBTI is obtained according to the deltaNIT total density, and an NBTI degradation model based on geometric construction analysis is obtained. The actual distribution situation of the interface traps produced by an NBTI effect is incorporated in the model, accordingly the total density of interface trap charges produced in the MOS device can be accurately calculated, thus a threshold voltage degradation model is obtained, few fitting parameters are required, the applicability is wide, and the model provides more accurate precision for device reliability.

A method for operating nonvolatile memory element includes exerting negative bias at gate electrode, utilizing-FN tunneling mechanism to make electron inject into electric charge storage layer from gate electrode of memory unit and via multiplayer tunneling dielectric structure for causing initial voltage-rise of memory unit, exerting a positive bias on gate electrode, utilizing + FN tunneling mechanism to make electric cavity inject into said electric charge layer from said gate electrode of memory unit and via said tunneling dielectric structure for causing initial voltage-drop of memory unit.

The invention discloses a manufacturing method of an NROM and a device thereof. The method comprises the following steps of: forming a source electrode and a drain electrode below a working surface of a semiconductor substrate; etching a chute on the semiconductor substrate between the source electrode and the drain electrode, and infusing silicon ion on the chute section of the semiconductor substrate so as to ensure non-crystallization of the semiconductor substrate on the surface of the chute; forming an ONO insulation layer on the surfaces of the semiconductor substrate, the source electrode and the drain electrode, wherein the ONO insulation layer is projected corresponding to the section of the chute and is inlayed in the chute of the semiconductor substrate; and forming a control grid on the surface of the ONO insulation layer between the source electrode and the drain electrode. Compared with the NROM device with reduced size in equal proportion, the NROM device during operation relatively lengthens the effective chute and solves all kinds of problems resulting from reducing the length of the chute, such as declination of the threshold voltage of the device, higher leakagecurrent and interference generated between two locations.

Methods and systems for computing threshold voltage degradation of transistors in an array of memory cells are disclosed. In accordance with one method, a process that models an expected usage of the array is selected. In addition, a hardware processor can run the process to populate the array with data over time to simulate the expected usage of the array. The method further includes compiling data that detail different durations at which each of the memory cells in the array stores 1 or at which each of the memory cells in the array stores 0. For each separate grouping of memory cells that share a common duration of the different compiled durations, a threshold voltage degradation is determined for each transistor in the corresponding grouping of cells based on at least one biased temperature instability model.

There are provided a substrate including an oxide TFT having improved initial threshold voltage degradation characteristics included in a driving circuit of a liquid crystal display (LCD) device, a method for fabricating the same, and a driving circuit for an LCD device using the same. The substrate including an oxide thin film transistor (TFT) includes: a base substrate divided into a pixel region and a driving circuit region; and a plurality of TFTs formed on the base substrate, wherein an initial threshold voltage of at least one of the plurality of TFTs formed in the driving circuit region is positive-shifted to have a predetermined level.

The invention discloses an arc-shaped fin top forming method and a fin field effect transistor. The method comprises the following steps that: a fin structure is provided; atomic layer etching is carried out on the top of the fin structure, and whether etching is carried out again is determined according to the etching amount of the fin structure; if yes, atomic layer etching on the top of the fin structure continues to be executed, and whether the etching process is conducted again or not is determined according to the etching amount of the fin structure; and if not, etching is stopped. The atomic layer etching process is circularly executed on the top of the fin structure to form the arc-shaped fin top, although the etching rate of the circulating process is lower than that of an existing mode, the circulating process does not damage the surface, and the pattern size and the loading density can be minimized. As the surface is not damaged, charge trapping is not formed, and the electrical characteristics of the device are not influenced by the reduction of the gate threshold voltage of the device.

The present invention proposes an analytical method for NBTI degradation prediction under a low-frequency AC stress mode, comprising the following steps: Step 1: Obtain the NBTI degradation reaction-diffusion model parameters of p-MOSFET devices; Step 2: Based on the basic reaction-diffusion theory and H 2 The locking effect of the NBTI DC stress / recovery phase is obtained; Step 3: Based on the fast capture / release of electrons, an iterative analytical model is obtained to describe the low-frequency AC stress mode of the NBTI at any moment and the pressure in the AC cycle The non-iterative analytical model of NBTI at the end of the ON phase and the end of the recovery OFF phase; Step 4: According to the analytical model, predict the threshold voltage degradation of the NBTI low-frequency AC stress degradation mode of the p-MOSFET device.