33 results about "Positive bias temperature instability" patented technology

The invention discloses a forming method of a metal gate, a forming method of an MOS (metal oxide semiconductor) transistor and a forming method of a CMOS (complementary metal oxide semiconductor) structure. The forming method of the metal gate comprises the following steps: after removing a pseudo polycrystalline silicon gate and forming a groove, forming high-K gate medium layers at the bottom and on the side wall of the groove, fluoridizing the high-K gate medium layers, and forming a function layer and a metal layer on the surfaces of the high-K gate medium layers. As fluorine bonds such as fluorine-silicon bonds and fluorine-hafnium bonds can be formed among the high-K gate medium layers and a semiconductor substrate after fluoridization and the bond energy of the fluorine bonds is higher than that of original hydrogen bonds, the instability of the negative bias temperature of a device is reduced; as fluorine is strong in oxidability, oxygen vacancies can be prevented from generating donor level in a band gap and becoming positively charged oxygen vacancies, the oxygen vacancies are passivated, and the instability of the positive bias temperature of the device is reduced.

A method, test circuit and test system provide measurements to accurately characterize threshold voltage changes due to negative bias temperature instability (NBTI) and positive bias temperature instability (PBTI). Both the bias temperature instability recovery profile and / or the bias temperature shifts due to rapid repetitions of stress application can be studied. In order to provide accurate measurements when stresses are applied at intervals on the order of tens of nanoseconds while avoiding unwanted recovery, and / or to achieve recovery profile sampling resolutions in the nanosecond range, multiple delay or ring oscillator frequency measurements are made using a delay line that is formed from delay elements that have delay variation substantially caused only by NBTI or PBTI effects. Devices in the delay elements are stressed, and then the delay line / ring oscillator is operated to measure a threshold voltage change for one or more measurement periods on the order of nanoseconds.

A method and test circuit provide measurements to aid in the understanding of time-varying threshold voltage changes such as negative bias temperature instability and positive bias temperature instability. In order to provide accurate measurements during an early stage in the threshold variation, a current generating circuit is integrated on a substrate with the device under test, which may be a device selected from among an array of devices. The current generating circuit may be a current mirror that responds to an externally-supplied current provided by a test system. A voltage source circuit may be included to hold the drain-source voltage of the transistor constant, although not required. A stress is applied prior to the measurement phase, which may include a controllable relaxation period after the stress is removed.

The invention belongs to a integrated circuit reliability test technology field and especially relates to a multifunctional test circuit of integrated circuit stress degradation and a test method thereof. A core part of the test circuit takes an annular oscillator as a basis. Several auxiliary transistors, switch transistors and control terminals are added. By using the circuit and the method of the invention, a negative bias temperature instability, a positive bias temperature instability, hot hole injection or hot electron injection stress can be applied to pMOSFETs or nMOSFETs in a ring vibration inverter respectively; a ring oscillator is in a normal oscillation and stress oscillation state; the pMOSFETs or nMOSFETs of the inverter in the ring oscillator is in a measuring state of a charge pump. The degradation of the MOSFETs in the ring vibration inverter can be shown through changes of a ring oscillator oscillation frequency after the stress and can be shown through the changes of a CP current (Icpp or Icpn) of the pMOSFETs or nMOSFETs in the ring oscillator.