33 results about "Positive bias temperature instability" patented technology

A ring oscillator has an odd number of NOR-gates greater than or equal to three, each with first and second input terminals, a voltage supply terminal, and an output terminal. The first input terminals of all the NOR-gates are interconnected, and each of the NOR-gates has its output terminal connected to the second input terminal of an immediately adjacent one of the NOR-gates. During a stress mode, a voltage supply and control block applies a stress enable signal to the interconnected first input terminals, and an increased supply voltage to the voltage supply terminals. During a measurement mode, this block grounds the interconnected first input terminals, and applies a normal supply voltage to the voltage supply terminals. Also included are an analogous NAND-gate based circuit, a circuit combining the NAND- and NOR-aspects, a circuit with a ring oscillator where the inverters may be coupled directly or through inverting paths, and circuits for measuring the bias temperature instability effect in pass gates.

Various embodiments provide transistors and their fabrication methods. An exemplary method for forming a transistor includes removing a dummy gate to form a trench over a semiconductor substrate. A high-k dielectric layer can be conformally formed on surface of the trench and then be fluorinated to form a fluorinated high-k dielectric layer. A functional layer can be formed on the fluorinated high-k dielectric layer and a metal layer can be formed on the functional layer to fill the trench with the metal layer. Due to fluorination of the high-k dielectric layer, negative bias temperature instability of the formed transistor can be reduced and oxygen vacancies can be passivated to reduce positive bias temperature instability of the transistor.

A method, test circuit and test system provide measurements to accurately characterize threshold voltage changes due to negative bias temperature instability (NBTI) and positive bias temperature instability (PBTI). Both the bias temperature instability recovery profile and/or the bias temperature shifts due to rapid repetitions of stress application can be studied. In order to provide accurate measurements when stresses are applied at intervals on the order of tens of nanoseconds while avoiding unwanted recovery, and/or to achieve recovery profile sampling resolutions in the nanosecond range, multiple delay or ring oscillator frequency measurements are made using a delay line that is formed from delay elements that have delay variation substantially caused only by NBTI or PBTI effects. Devices in the delay elements are stressed, and then the delay line/ring oscillator is operated to measure a threshold voltage change for one or more measurement periods on the order of nanoseconds.

A method and test circuit provide measurements to aid in the understanding of time-varying threshold voltage changes such as negative bias temperature instability and positive bias temperature instability. In order to provide accurate measurements during an early stage in the threshold variation, a current generating circuit is integrated on a substrate with the device under test, which may be a device selected from among an array of devices. The current generating circuit may be a current mirror that responds to an externally-supplied current provided by a test system. A voltage source circuit may be included to hold the drain-source voltage of the transistor constant, although not required. A stress is applied prior to the measurement phase, which may include a controllable relaxation period after the stress is removed.

The invention provides bias voltage temperature instability detection circuit and detection method. The bias voltage temperature instability detection circuit comprises an odd number of fundamental oscillation units. Each fundamental oscillation unit comprises a first transistor, a second transistor, a first control transistor, a second control transistor, an input end and an output end. The detection circuit further comprises third transistors which are located between adjacent fundamental oscillation units. The fundamental oscillation units and the third transistors are connected in series to form an annular oscillator. According to the embodiment of the invention, the bias voltage temperature instability detection circuit can respectively detect the degree of threshold voltage degradation, which is caused by negative bias voltage temperature instability, of a PMOS transistor and the degree of threshold voltage degradation, which is caused by positive bias voltage temperature instability, of an NMOS transistor; by using the third transistors, the degree of threshold voltage degradation, which is caused by bias voltage temperature instability, of an MOS transistor can be amplified; and the final detection result is sensitive and the detection precision is high.

The invention provides a method and a system for extracting a semiconductor defect level. The method comprises steps: through a positive bias temperature instability test, the threshold voltage of an nMOS device after applying gate stress voltage and different gate recovery voltage is acquired; according to the shift of the threshold voltage of the nMOS device after applying the different gate recovery voltage relative to applying the gate stress voltage, the defect surface density of a gate dielectric layer corresponding to the different gate recovery voltage is acquired, and the corresponding relationship between the different gate recovery voltage and the defect surface density of the gate dielectric layer is acquired; the corresponding relationship between the different gate recovery voltage and a defect level is acquired; and the corresponding relationship between the defect surface density of the gate dielectric layer and the defect level is acquired. According to the method provided by the invention, the relationship between the defect level and the defect surface density of the gate dielectric layer can be extracted, and the device performance and the reliability can be improved.

The invention discloses a bias voltage temperature instability testing circuit which comprises a circular vibrator circuit. The vibrator circuit comprises n grades of testing circuits which are the same in structure. Each testing circuit comprises a first node, a second node and a third node. The third node of each testing circuit is connected with the first node of a former testing circuit. Each testing circuit comprises a PMOS tube to be tested, an NMOS tube to be tested, a switch PMOS tube, a switch NMOS tube and at least one pair of partial pressure PMOS tube and partial pressure NMOS tube, wherein the PMOS tube to be tested and the NMOS tube to be tested are complementary, the switch PMOS tube and the switch NMOS tube are complementary, and the partial pressure PMOS tube and the partial pressure NMOS tube are complementary. The invention further discloses a testing method for the bias voltage temperature instability testing circuit. The method comprises the steps of providing the bias voltage temperature instability testing circuit, testing the negative bias pressure temperature instability of the PMOS tube to be tested and testing the positive bias pressure temperature instability of the NMOS tube to be tested. The bias voltage temperature instability testing circuit can test the negative bias pressure temperature instability of the PMOS tube to be tested and the positive bias pressure temperature instability of the NMOS tube to be tested.

The invention provides a semiconductor device, a manufacturing method thereof and an electronic device. The method comprises the steps of providing a semiconductor substrate, wherein a gate groove isformed on the semiconductor substrate; and forming a high-k dielectric layer at the bottom of the gate groove and also comprises the following steps of performing first annealing under an atmosphere containing a hydrogen element before the high-k dielectric layer is formed so that a suspension bond exposed out of the gate groove and in the semiconductor substrate is passivated, and/or performing second annealing after the high-k dielectric layer is formed so that oxygen vacancy in the high-k dielectric layer is passivated. According to the manufacturing method, first annealing is performed under the atmosphere containing the hydrogen element before the high-k dielectric layer is formed so that the exposed suspension bond in the semiconductor substrate is passivated, hot carrier injection (HCI) and negative bias temperature instability (NBTI) of the device are improved, second annealing is performed after the high-k dielectric layer is formed so that the oxygen vacancy in the high-k dielectric layer is passivated, positive bias temperature instability (PBTI) is further improved, and the performance and the reliability of the device are improved.

A logic circuit is operated in a normal mode, with a supply voltage coupled to a supply rail of the logic circuit, and with a ground rail of the logic circuit grounded; It is determined that at least a portion of the logic circuit has experienced degradation due to bias temperature instability. Responsive to the determining, the logic circuit is operated in a power napping mode, with the supply voltage coupled to the ground rail of the circuit, with the supply rail of the circuit grounded, and with primary inputs of the circuit toggled between logical zero and logical one at low frequency. A logic circuit and corresponding design structures are also provided.

Provided are a restoring circuit and restoring method against positive bias temperature instability. The restoring circuit comprises a to-be-restored N-channel metal oxide semiconductor (NMOS) transistor and a restoring unit. A grid electrode of the to-be-restored NMOS transistor is connected with the restoring unit. According to the restoring unit, a grid electrode of a switch transistor is connected with a signal input end, a drain electrode of the switch transistor is connected with a first voltage end, the first voltage end provides a negative first working voltage, a substrate of the switch transistor is connected with a second voltage end, a source electrode of the switch transistor is connected with one end of a second resistor, the other end of the second resistor is connected with a signal output end, one end of a first resistor is connected with a signal input end, and the other end of the first resistor is connected with the signal output end. Due to the fact that the voltage of the first voltage end is negative, by adjusting resistance values of the first resistor and the second resistor, grid electrode voltage applied to the to-be-restored NMOS transistor can be negative pressure, and good positive bias temperature instability (PBTI) characteristic restoration effect can be achieved.

A method and apparatus for calculating delay timing values for at least a part of an integrated circuit design. The method comprises applying a first Negative/Positive Bias Temperature Instability compensation margin to delay values for elements within the at least part of the IC design, identifying at least one lower-rate switching element within the at least part of the IC design, and applying at least one further, increased N/PBTI compensation margin to the delay value(s) for the at least one identified lower-rate switching element.