170results about How to "High power supply voltage" patented technology

Disclosed herein is a display device including a pixel array unit and a control unit.

Various circuit techniques for implementing ultra high speed circuits use current-controlled CMOS (C³MOS) logic fabricated in conventional CMOS process technology. An entire family of logic elements including inverter/buffers, level shifters, NAND, NOR, XOR gates, latches, flip-flops and the like are implemented using C³MOS techniques. Optimum balance between power consumption and speed for each circuit application is achieve by combining high speed C³MOS logic with low power conventional CMOS logic. The combined C³MOS/CMOS logic allows greater integration of circuits such as high speed transceivers used in fiber optic communication systems. The C³MOS structure enables the use of a power supply voltage that may be larger than the voltage required by the CMOS fabrication process, further enhancing the performance of the circuit.

A ring oscillator has an odd number of NOR-gates greater than or equal to three, each with first and second input terminals, a voltage supply terminal, and an output terminal. The first input terminals of all the NOR-gates are interconnected, and each of the NOR-gates has its output terminal connected to the second input terminal of an immediately adjacent one of the NOR-gates. During a stress mode, a voltage supply and control block applies a stress enable signal to the interconnected first input terminals, and an increased supply voltage to the voltage supply terminals. During a measurement mode, this block grounds the interconnected first input terminals, and applies a normal supply voltage to the voltage supply terminals. Also included are an analogous NAND-gate based circuit, a circuit combining the NAND- and NOR-aspects, a circuit with a ring oscillator where the inverters may be coupled directly or through inverting paths, and circuits for measuring the bias temperature instability effect in pass gates.

Various circuit techniques for implementing ultra high speed circuits use current-controlled CMOS (C³MOS) logic fabricated in conventional CMOS process technology. An entire family of logic elements including inverter/buffers, level shifters, NAND, NOR, XOR gates, latches, flip-flops and the like are implemented using C³MOS techniques. Optimum balance between power consumption and speed for each circuit application is achieve by combining high speed C³MOS logic with low power conventional CMOS logic. The combined C³MOS/CMOS logic allows greater integration of circuits such as high speed transceivers used in fiber optic communication systems. The C³MOS structure enables the use of a power supply voltage that may be larger than the voltage required by the CMOS fabrication process, further enhancing the performance of the circuit.

A Multi-Tile Power Management Integrated Circuit (MTPMIC) includes tiles including an MCU/ADC tile and a power manager tile. The power manager tile includes a set of Configurable Switching Power Supply Pulse Width Modulator (CSPSPWM) components. These components, in combination with other circuitry external to the integrated circuit, are configurable to form a selected one of a number of different switching power supply circuits. Upon power up, an internal regulator supplies power to the CSPSPWM. The CSPSPWM then controls the power supply to begin switching in a low frequency start-up mode. The CSPSPWM determines during start-up the current sensing method based on circuitry external to the integrated circuit. A supply voltage generated is then supplied via a conductor of a standardized bus to a processor in the MCU/ADC tile. The processor begins executing instructions, and as a result writes across the standardized bus to configure the various tiles of the MTPMIC.

A secondary-battery monitoring device capable of realizing highly reliable overcurrent detection and a battery pack having it are provided. When an overcurrent flowing to a secondary battery is to be detected by utilizing a current detection voltage generated via on-resistance of a discharge-control switch and a charge-control switch, a voltage correction circuit that generates a correction voltage having a characteristic varied by positive slope or negative slope along with increase in a power supply voltage is provided, and the correction voltage is added to the detection voltage or a reference power supply voltage with the polarity that cancels out the slope of voltage variation caused in the detection voltage, and then the voltage is input to a comparator circuit. In this manner, variation in the overcurrent determination current is reduced.

There is provided a sensor tag device capable of detecting event data by a sensor tag all the time even when no radio wave is received, saving power supply for a microprocessor, and enlarging the radio communication distance. The sensor tag device includes generation means 6 and 7 using one or more environmental changes, power supply voltage rise control means 8, and power supply synthesis means 9, and power is supplied to a microprocessor 12 and event data is stored in the microprocessor 12 when an event, i.e., an environmental change has occurred. A power receiving circuit having a transmission/reception antenna, a built-in power receiving circuit, and the microprocessor and capable of bi-directional communication by radio waves is combined with a stab resonance RF boost circuit and a ladder boost rectification circuit.

A CPU sets an SPM driver in SPM start-up mode when a SPM is started up. At this time, a voltage selector applies, to a driver circuit, a voltage (high voltage) boosted by a voltage booster. A starter control circuit controls, during the period of an SPM start-up mode, the driver circuit with the high voltage applied thereto, thereby starting up the SPM. After the SPM has been started up, the CPU sets the SPM driver in PWM mode. At this time, the voltage selector switches the voltage applied to the driver circuit, from the boosted voltage to the voltage (low voltage) of a power supply. During the period of the PWM mode, a PWM circuit controls the driver circuit with the low voltage applied thereto, so as to rotate the SPM at a rated speed.

A charging control apparatus comprising: a voltage control unit in a charging apparatus configured to control generation of an output voltage and a power supply voltage, the charging apparatus being an apparatus configured to generate, from a voltage of an input power supply applied through a relay, the output voltage for charging a battery and the power supply voltage for control; and a relay control unit operated by the power supply voltage, the relay control unit configured to drive the relay so as to stop applying the voltage of the input power supply to the charging apparatus, when detecting a standby state in which the battery is not being charged, and drive the relay so as to increase the power supply voltage by applying the voltage of the input power supply to the charging apparatus, when the power supply voltage decreases below a predetermined level.

A rise in the power supply voltage as a result of a sudden speed reducing command causing the motor current to flow to the power supply is prevented. The motor drive device has a drive signal generating unit for generating a drive signal by an energizing control unit, PWM control unit, and oscillation unit; a drive unit for producing drive power to drive the motor based on the drive signal; a torque control signal generating unit for generating a torque control signal specifying the motor torque; a speed detection unit for detecting the rotational speed of the motor and generating a rotational speed signal denoting motor speed information; and a decision unit for generating a speed difference detection signal denoting the difference between the torque control signal and the rotational speed signal. The drive signal generating unit is controlled based on the speed difference detection signal.