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Method for forming NMOS (N-channel Metal Oxide Semiconductor) transistor

A technology of transistors and barrier layers, applied in the fields of semiconductor devices, semiconductor/solid-state device manufacturing, electrical components, etc., can solve the problems of NMOS transistor threshold voltage drop and other problems, and achieve the effect of improving reliability

Active Publication Date: 2014-09-24
SEMICONDUCTOR MANUFACTURING INTERNATIONAL (BEIJING) CORP
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  • Summary
  • Abstract
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  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

[0011] The problem solved by the present invention is to provide a method for forming an NMOS transistor to solve the problem of the threshold voltage drop of the NMOS transistor formed by the stress memory process

Method used

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  • Method for forming NMOS (N-channel Metal Oxide Semiconductor) transistor
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  • Method for forming NMOS (N-channel Metal Oxide Semiconductor) transistor

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Embodiment Construction

[0034] The prior art uses stress memorization techniques (SMT) to increase the compressive stress in the vertical direction of the channel region, but the threshold voltage of the NMOS transistor formed by the method is significantly higher than the standard threshold voltage value to be formed. decline.

[0035] refer to figure 1 and to figure 2 The inventors found that after the stress layer 005 was formed, the concentration of dopant ions in the source / drain region decreased more than the concentration of dopant ions before the formation of the stress layer 005, which reduced the difficulty of opening the channel region, In turn, the threshold voltage and the standard threshold voltage to be formed are significantly lowered.

[0036] The inventors further found that the process environment for forming the stress layer 005 will cause the formed stress layer 005 to contain hydrogen. For example, when the chemical vapor deposition method is used to form the stress layer 00...

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Abstract

The invention provides a method for forming an NMOS (N-channel Metal Oxide Semiconductor) transistor. The method comprises the following steps of: providing a substrate and a grid structure located on the substrate; taking the grid structure as a mask to carry out ion implantation on the substrate, and forming a source area and a drain area in the substrate at the both sides of the grid structure; forming a stopping layer on the exposed surfaces of the substrate and the grid structure; forming a stress layer on the stopping layer, wherein the stopping layer is used for preventing hydrogen elements used in the forming environment of the stress layer from entering the source area and the drain area; carrying out heat treatment on the source area and the drain area; and removing the stopping layer and the strain layer. According to the method disclosed by the invention, the compact stopping layer is formed on the surfaces of the substrate and the grid structure before the stress layer is formed, so as to prevent the hydrogen elements used in the forming environment of the stress layer from entering the source area / drain area in the substrate. Therefore, the problem of descending of threshold voltage, caused when the diffusion of doped ions in the source area / drain area is enhanced by the hydrogen elements, is solved, the reliability of the threshold voltage is improved, and the property reliability of the NMOS transistor is further improved.

Description

technical field [0001] The invention relates to the field of semiconductor manufacturing, in particular to a method for forming an NMOS transistor. Background technique [0002] It is well known that mechanical stress can change the energy gap and carrier mobility of silicon materials, and recently, mechanical stress has played an increasingly important role in affecting the performance of MOSFETs. If the stress can be properly controlled, the mobility of carriers (electrons in n-channel transistors, holes in p-channel transistors) is increased, and the drive current is increased, so stress can greatly improve the performance of transistors. [0003] The prior art uses stress liner technology to improve the mechanical stress performance of transistors. For example, a tensile stress liner (tensile stress liner) is formed on the NMOS transistor, and a compressive stress liner (compressive stress liner) is formed on the PMOS transistor, thereby increasing the driving current o...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): H01L21/336H01L21/28H01L21/265
Inventor 鲍宇张彬
Owner SEMICONDUCTOR MANUFACTURING INTERNATIONAL (BEIJING) CORP
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