Manufacturing method of NROM and device thereof

Abstract

The invention discloses a manufacturing method of an NROM and a device thereof. The method comprises the following steps of: forming a source electrode and a drain electrode below a working surface of a semiconductor substrate; etching a chute on the semiconductor substrate between the source electrode and the drain electrode, and infusing silicon ion on the chute section of the semiconductor substrate so as to ensure non-crystallization of the semiconductor substrate on the surface of the chute; forming an ONO insulation layer on the surfaces of the semiconductor substrate, the source electrode and the drain electrode, wherein the ONO insulation layer is projected corresponding to the section of the chute and is inlayed in the chute of the semiconductor substrate; and forming a control grid on the surface of the ONO insulation layer between the source electrode and the drain electrode. Compared with the NROM device with reduced size in equal proportion, the NROM device during operation relatively lengthens the effective chute and solves all kinds of problems resulting from reducing the length of the chute, such as declination of the threshold voltage of the device, higher leakagecurrent and interference generated between two locations.

Description

technical field [0001] The invention relates to a semiconductor manufacturing method and its device, in particular to a NROM manufacturing method and its device. Background technique [0002] NROM (Nitride Read-Only Memory) is a non-volatile read-only memory that uses the silicon nitride layer in the ONO (bottom oxide layer-silicon nitride layer-top oxide layer) insulating layer as a memory unit, using its Inherent physical properties, each memory cell contains two bits (Bit) to store information, compared with other non-volatile semiconductor memory devices, it has a higher storage density, and because it stores less charge, it has a higher program and erase speeds. [0003] see figure 1 , figure 1 It is a schematic diagram of NROM in the prior art. The NROM of the prior art includes: a semiconductor substrate 1, a source 2 and a drain 3 respectively formed at both ends of the semiconductor substrate 1, and on the surface of the semiconductor substrate 1 between the sou...

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Problems solved by technology

[0006] One: Due to the shortening of the channel length, the threshold voltage of the device decreases and the leakage current is higher;

[0007] Two: Due to the shortening of the channel length, interference is formed between the two bits;

[0008] Three: Due to the shortening of the channel length, in the stage of programming using NROM, after high temperature baking, the threshold voltage will further drop

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