40 results about "Substrate doping" patented technology

A device formed from a method of fabricating a fine metal silicide layer having a uniform thickness regardless of substrate doping. A planar vacancy is created by the separation of an amorphousized surface layer of a silicon substrate from an insulating layer, a metal source enters the vacancy through a contact hole through the insulating layer connecting with the vacancy, and a heat treatment converts the metal in the vacancy into metal silicide. The separation is induced by converting the amorphous silicon into crystalline silicon.

The invention discloses an array substrate doping method and doping equipment. The method includes the following steps: providing an array substrate on which a region to be heavily doped, a region to be lightly doped and a channel region to be doped are defined; forming a photoresist layer on the array substrate through a photolithography process, wherein a first photoresist part is formed on the photoresist layer corresponding to the region to be heavily doped, a second photoresist part is formed on the photoresist layer corresponding to the region to be lightly doped, a third photoresist part is formed on the photoresist layer corresponding to the channel region to be doped, the first photoresist part is thinner than the second photoresist part, and the second photoresist part is thinner than the third photoresist part; carrying out a one-time doping in the region to be heavily doped, the region to be lightly doped and the channel region to be doped via the photoresist layer, so as to form a heavily doped region, a lightly doped region and a doped channel region at a time respectively corresponding to the region to be heavily doped, the region to be lightly doped and the channel region to be doped. With the steps, one-time doping is realized in the region to be heavily doped, the region to be lightly doped and the channel region to be doped on the array substrate; the process is simplified; the cost is reduced.

This invention relates to a method and resulting structure, wherein a DRAM may be fabricated by using silicon midgap materials for transistor gate electrodes, thereby improving refresh characteristics of access transistors. The threshold voltage may be set with reduced substrate doping requirements. Current leakage is improved by this process as well.

The invention discloses a double-conduction semiconductor component. The double-conduction semiconductor component comprises a semiconductor substrate, a first substrate doping area, a second substrate doping area and a grid insulation layer, wherein the semiconductor substrate is provided with a first conduction type, and both the first substrate doping area and the second substrate doping area are provided with second conduction types. The semiconductor substrate is provided with a first groove, the first substrate doping area and the second substrate doping area are respectively arranged in the semiconductor substrate on two sides of the first groove, the grid insulation layer covers the surface of the first groove and is provided with a first part, a second part and a third part, wherein the first part is adjacent to the first substrate doping area, the second part is adjacent to the second substrate doping area, and the third part is arranged at a turning position of the bottom and the side wall of the first groove. The thickness of each of the first part and the second part is smaller than that of the third part. Therefore, withstand voltage of the double-conduction semiconductor component can be increased.

Disclosed is a conductive laminated body, and a method for preparing the same, wherein the conductive laminated body including: a substrate; a zinc oxide-based thin film doped with an element M; and an interlayer including an oxide M′2O3, which is interposed between the substrate and the zinc oxide-based thin film. The disclosed conductive laminated body includes a metal oxide interlayer of an oxidation number +3, between a substrate and a zinc oxide layer. Therefore, it is possible to improve electrical properties of a transparent conductive thin film, especially, a resistivity property, and to minimize the unevenness in electrical properties between a middle portion and a circumferential portion on the surface of the thin film in sputtering deposition. Also, in deposition of a zinc oxide film, in addition to inert gas such as argon gas, the use of hydrogen gas can improve the concentration of electrons, and herein, the interposition of an interlayer including a metal oxide, between the substrate and the zinc oxide-based transparent conductive film, allows the heat-resistance / moisture-resistance stability and the uniformity of electrical properties.

Short-circuit current, maximum power, and open circuit voltage during a single flash are determined by varying intensity, voltage, and current. An apparatus determines the substrate doping and the series resistance of the solar cell. The series resistance of the cell is determined from a voltage step from the maximum power voltage operating point to the open-circuit condition. Methods are described for determining the substrate doping from stepping or sweeping the voltage. The first uses a voltage step and finds the change in charge that results. This determines a unique doping if the series resistance is known. The second uses data for a case of varying current, voltage, and light intensity, and compares this data to the case of varying voltage and intensity with no current. By transposing both cases into the steady state, agreement between the two data sets is found for unique doping and series resistance values.

A phonon-regulated indirect bandgap semiconductor material lateral electrical injection light-emitting device, comprising: a p-type or n-type indirect bandgap semiconductor material substrate; an n heavily doped layer made on one side of the substrate, the It is the source region of the device; a p heavily doped layer is made on the other side of the substrate, which is the drain region of the device; a negative electrode is made on the n heavily doped layer; a positive electrode is made on the p heavily doped layer; An active region is made in the middle of the substrate; a dielectric layer or an indirect band gap semiconductor material layer is made on the active region; a gate is made on the dielectric layer; a back electrode is made on the bottom of the substrate; The heavily doped layer, the p heavily doped layer and the active region are embedded with nanoscale silicon dioxide, silicon nitride, silicon oxynitride nanoparticles or nanoholes.

The invention relates to a power LDMOS device with a junction field plate, and belongs to the technical field of power semiconductor devices. According to the power LDMOS device with the junction field plate, a buried layer opposite to a substrate doping type is formed on a substrate of a conventional LDMOS device, and the junction field plate formed by a PN junction is formed in the surface of a device drifting area. The power LDMOS device with the junction field plate uses PN junction electric field distribution in the junction field plate for modulating a device surface electric field, the distribution of the device surface electric field is made to be more even, the insufficiency of a peak of a tail end electric filed of a metal field plate can be effectively avoided, and breakdown performance of the device is improved. Under the reverse blocking state, the junction field plate has an auxiliary exhaustion function for the drifting area, the doping level of the drifting area can be improved to a large extent, and the on-resistance of the device is reduced. Meanwhile, reverse currents are small when reverse bias of the PN junction in the junction field plate occurs, the fact that leakage currents in the field plate are reduced is benefited, and the buried layer in the substrate can effectively improve the voltage endurance property of the device. The device has the advantages of being high in voltage, low in power consumption, low in cost and easy to integrate, and is suitable for power integrated circuits and radio frequency power integrated circuits.

The invention relates to a substrate doping structure and a formation method thereof. The method comprises steps of providing a substrate including an isolation region and a first doping well region;forming first graphical mask layers which are exposed to the isolation region and the first doping well region on the surface of the substrate; by taking the first graphical mask layers as masks, carrying out field injection on the substrate and forming doping regions in the isolation region and the first doping well region; by taking the first graphical mask layers as masks, carrying out first doping ion injection on the substrate and forming first doping regions in the isolation region and the first doping well region; forming second graphical mask layers exposed to the first doping well region on the surface of the substrate; and by taking the second graphical mask layers as masks, carrying out second doping ion injection on the substrate and forming second doping regions in the first doping well region, wherein the first doping regions are arranged in the second doping regions. According to the invention, device performance can be improved with no need to increase the quantity of light covers.

The invention provides a semiconductor substrate testing structure and testing method for monitoring integrated passive devices. The test structure for monitoring a semiconductor substrate for integrating passive devices according to the present invention includes: the two ends of the semiconductor circuit on the semiconductor substrate that are connected to the two ends of the inductance, capacitance and resistance tester are separated by a specific distance. The first metal wire and the second metal wire, wherein a test signal is added to one end of the LCR tester to obtain a C-V curve, and the doping concentration of the semiconductor substrate is determined through the C-V curve. According to the test structure for monitoring semiconductor substrates used for integrated passive devices, the C-V curves reflect the characteristics of metal-oxide-substrate capacitors, and the characteristics of metal-oxide-substrate capacitors are as the semiconductor substrate is doped. The C-V curve reflects the doping concentration of the semiconductor substrate. Furthermore, the change of the resistivity of the semiconductor substrate can be judged by the doping concentration of the semiconductor substrate.

Embodiments of the present application provide an image sensor device structure and a forming method thereof. The image sensor device structure includes a substrate, and the substrate is doped with impurities of a first conductivity type. The image sensor device structure includes a photo-sensing region formed in the substrate, and the photo-sensing region is doped with impurities of a second conductivity type different from the first conductivity type. The image sensor device structure further includes a doping region extending into the photo-sensing region, and the doping region is doped with impurities of the first conductivity type. The image sensor device structure also includes a plurality of color filters formed on the doped regions.

The invention discloses a groove type field effect positive feedback transistor based on a semiconductor substrate and a preparation method thereof. The positive feedback transistor uses a groove type gate oxide layer structure to improve the defects of the planar gate oxide layer positive feedback transistor. By introducing key The doping of the channel region and the inverse substrate doping and low drain doping region of the channel region form the special energy band structure required by the positive feedback mechanism, thereby achieving electrical properties similar to ordinary positive feedback transistors In addition, the positive feedback transistor has a symmetrical physical structure similar to that of a MOSFET, and can be formed on the channel region by a self-aligned ion implantation process similar to a MOSFET under the masking effect of the positive gate and the gate spacer Low drain doping region and cathode region / anode region doping; the positive feedback transistor preparation process of the present invention is compatible with traditional CMOS, increases gate oxide layer capacitance, increases charge retention time, prolongs data storage time, and improves the Device performance as memory.