Substrate doping structure and method for forming the same

A technology of substrates and doped regions, applied in semiconductor devices, electrical components, circuits, etc., can solve the problems of increasing the cost of memory technology, and achieve the effect of improving performance and reducing leakage current.

Active Publication Date: 2020-12-11
YANGTZE MEMORY TECH CO LTD
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

In order to perform this field implantation process, it is necessary to add an additional mask to define the field doping area, which leads to an increase in the process cost of the memory

Method used

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  • Substrate doping structure and method for forming the same
  • Substrate doping structure and method for forming the same
  • Substrate doping structure and method for forming the same

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Embodiment Construction

[0021] The specific implementation of a substrate doping structure and its forming method provided by the present invention will be described in detail below with reference to the accompanying drawings.

[0022] Please refer to figure 1 , a substrate 100 is provided, and the substrate 100 includes an isolation region I and a first doped well region II.

[0023] The substrate 100 may be a semiconductor material, such as a single-crystal silicon substrate, a single-crystal germanium substrate, an SOI (silicon-on-insulator) or a GOI (germanium-on-insulator) substrate, etc., and the substrate 100 may also be For P-type doping or N-type doping. A person skilled in the art can select a suitable material as the substrate according to actual requirements, which is not limited herein.

[0024] The substrate 100 is used to form a memory, including a storage area and a peripheral circuit area, and the peripheral circuit area is used to form a peripheral circuit to control the memory c...

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PUM

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Abstract

The invention relates to a substrate doping structure and a formation method thereof. The method comprises steps of providing a substrate including an isolation region and a first doping well region;forming first graphical mask layers which are exposed to the isolation region and the first doping well region on the surface of the substrate; by taking the first graphical mask layers as masks, carrying out field injection on the substrate and forming doping regions in the isolation region and the first doping well region; by taking the first graphical mask layers as masks, carrying out first doping ion injection on the substrate and forming first doping regions in the isolation region and the first doping well region; forming second graphical mask layers exposed to the first doping well region on the surface of the substrate; and by taking the second graphical mask layers as masks, carrying out second doping ion injection on the substrate and forming second doping regions in the first doping well region, wherein the first doping regions are arranged in the second doping regions. According to the invention, device performance can be improved with no need to increase the quantity of light covers.

Description

technical field [0001] The invention relates to the field of semiconductor technology, in particular to a substrate doping structure and a forming method thereof. Background technique [0002] In recent years, the development of flash memory (Flash Memory) is particularly rapid. The main feature of flash memory is that it can keep stored information for a long time without power on, and has the advantages of high integration, fast access speed, easy erasing and rewriting, etc. Has been widely used. 3D NAND Flash memory is a new type of product based on planar NAND flash memory. The main feature of this product is to stack multiple layers of data storage units vertically, transforming the planar result into a three-dimensional structure, which can create a storage capacity that is several times higher than that of similar NAND technologies. times the storage device. The technology enables higher storage capacity in less space, resulting in significant cost savings, reduced...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): H01L21/265H01L21/266H01L29/10
CPCH01L21/26506H01L21/26513H01L21/266H01L29/1079
Inventor 许文山方欣欣
Owner YANGTZE MEMORY TECH CO LTD
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