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Grooved Field Effect Positive Feedback Transistor Based on Semiconductor Substrate and Fabrication Method

A groove-type, field-effect technology, which is applied in semiconductor/solid-state device manufacturing, semiconductor devices, electrical components, etc., can solve the problem of storage time reduction, increase charge retention time, increase gate oxide layer capacitance, and improve performance. Effect

Active Publication Date: 2021-09-28
FUDAN UNIV
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

In addition, the reduction in capacitance will lead to a decrease in storage time, which is a disadvantage that cannot be ignored for applications in high-performance dynamic memories

Method used

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  • Grooved Field Effect Positive Feedback Transistor Based on Semiconductor Substrate and Fabrication Method
  • Grooved Field Effect Positive Feedback Transistor Based on Semiconductor Substrate and Fabrication Method
  • Grooved Field Effect Positive Feedback Transistor Based on Semiconductor Substrate and Fabrication Method

Examples

Experimental program
Comparison scheme
Effect test

Embodiment 1

[0104] The substrate 1 is weakly P-doped, the channel region 2 is N-doped, and the low-drain doped region is P-doped. The cathode region 9 is heavily doped with N+ type and the anode region 10 is heavily doped with P+ type.

[0105] In the step S2, the doping concentration of the channel region 2 is 10 15 cm -2 to 10 19 cm -2 Between, the thickness of the channel region 2 is between 50nm and 1000nm.

[0106] In the step S3, the etching window of the groove structure is opened by photolithography, and the groove structure is formed by dry etching or wet etching. The dry etching generally uses fluorine-based or halogen gas, such as SF 6 、CHF 3 , HBr or Cl 2 etc. The wet etching generally uses TMAH and KOH solutions, the diameter of the groove structure is generally between 5nm and 200nm, and the depth is generally between 10nm and 1000nm.

[0107] In the step S4, the gate oxide layer 3 is deposited by atomic layer deposition, and the thickness of the gate oxide layer 3 i...

Embodiment 2

[0115] Such as image 3 As shown, the second embodiment is similar to the first embodiment, the difference is that the doping type of the second embodiment is an inverse doping, that is, the device in the second embodiment is a P-type device, and the device in the first embodiment is an N-type device . Wherein the substrate 1 is weakly N-type doped, the channel region 2 is P-type doped, and the ion implantation in the low-drain doped region is N-type doped. The cathode region 9 is doped with N+ type and the anode region 10 is doped with P+ type.

[0116] The specific implementation process flow is similar to the process flow of Example 1. It is only necessary to change the doping of the substrate 1 in step S1 to N-type. In step S6, arsenic or phosphorus is used for ion implantation to form a heavily N-type doped low-drain doped regions with a dose of 10 12 cm -2 to 10 14 cm -2 Between, the energy is between 1keV and 50keV. Others are similar to the first embodiment, and...

Embodiment 3

[0118] Such as Figure 4 As shown, the structure of the third embodiment is similar to the structure of the first embodiment, the difference lies in the formation of the cathode region 9 and the anode region 10 . In the third embodiment, the epitaxy of the cathode region 9 and the anode region 10 does not require in-situ doping and does not require a mask. After epitaxy, N+ and P+ doping is selectively formed in the epitaxial layers of the cathode region 9 and the anode region 10 by combining photolithography and ion implantation.

[0119] A method for preparing the semiconductor substrate-based recessed field effect positive feedback transistor according to this embodiment, the method includes:

[0120] T1. Prepare a weakly doped starting substrate 1 .

[0121] T2. Epitaxially growing a doped channel region 2 on the substrate 1 .

[0122] T3. Using a mask to form a groove structure at a preset position on the channel region 2 .

[0123] T4. Deposit a layer of groove-shape...

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Abstract

The invention discloses a groove type field effect positive feedback transistor based on a semiconductor substrate and a preparation method thereof. The positive feedback transistor uses a groove type gate oxide layer structure to improve the defects of the planar gate oxide layer positive feedback transistor. By introducing key The doping of the channel region and the inverse substrate doping and low drain doping region of the channel region form the special energy band structure required by the positive feedback mechanism, thereby achieving electrical properties similar to ordinary positive feedback transistors In addition, the positive feedback transistor has a symmetrical physical structure similar to that of a MOSFET, and can be formed on the channel region by a self-aligned ion implantation process similar to a MOSFET under the masking effect of the positive gate and the gate spacer Low drain doping region and cathode region / anode region doping; the positive feedback transistor preparation process of the present invention is compatible with traditional CMOS, increases gate oxide layer capacitance, increases charge retention time, prolongs data storage time, and improves the Device performance as memory.

Description

technical field [0001] The invention relates to the technical field of semiconductor devices, in particular to a groove-type field-effect positive-feedback transistor based on a semiconductor substrate and a preparation method thereof. Background technique [0002] For decades, the traditional one-transistor-capacitor dynamic random access memory (1T-1C DRAM) has shown good reliability and high integration (references: Song KW, Kim y, Kim H, Chung HW, et al. A 31ns random cycle VCat-based 4F2 DRAM with enhanced cell efficiency. Proc Symp vls Circuits 2009:132-3). For example, recently proposed popular dynamic memory devices, including capacitor-based IT-IC dynamic random access memory (DRAM) (reference: C.J.Radens, S.Kudelka, L.Nesbit, et al. "Anorthogonal 6F trench sidewall vertical device cell for 4 Gb / 16 Gb DRAM," inIEDM Tech.Dig., 2000, pp.349–352.), conventional 6-T SRAM (reference: L.Chang, D.M.Fried, J.Hergenrother , et al. "Stable SRAM cell design for the 32nmnode ...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): H01L29/78H01L29/10H01L29/36H01L29/423H01L21/336
CPCH01L29/1033H01L29/36H01L29/4236H01L29/42364H01L29/66492H01L29/7834H01L29/7838
Inventor 万景肖凯陈颖欣
Owner FUDAN UNIV
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