47 results about "MIS capacitor" patented technology

An integrated MIS capacitor has two substantially identical MIS capacitors. A first capacitor comprises a first region of a first conductivity type adjacent to a channel region of the first conductivity type in a semiconductor substrate. The semiconductor substrate has a second conductivity type. A gate electrode is insulated and spaced apart from the channel region of the first capacitor. The second capacitor is substantially identical to the first capacitor and is formed in the same semiconductor substrate. The gate electrode of the first capacitor is electrically connected to the first region of the second capacitor and the gate electrode of the second capacitor is electrically connected to the first region of the first capacitor. In this manner, the capacitors are connected in an anti-parallel configuration. A capacitor which has high capacitance densities, low process complexity, ambipolar operation, low voltage and temperature coefficient, low external parasitic resistance and capacitance and good matching characteristics for use in analog designs that can be integrated with existing semiconductor processes results.

Hydrogen gas sensors employ an epitaxial layer of the thermodynamically stable form of aluminum nitride (AlN) as the “insulator” in an MIS structure having a thin metal gate electrode suitable for catalytic dissociate of hydrogen, such as palladium, on a semiconductor substrate. The AlN is deposited by a low temperature technique known as Plasma Source Molecular Beam Epitaxy (PSMBE). When silicon (Si) is used the semiconducting substrate, the electrical behavior of the device is that of a normal nonlinear MIS capacitor. When a silicon carbide (SiC) is used, the electrical behavior of the device is that of a rectifying diode. Preferred structures are Pd / AlN / Si and Pd / AlN / SiC wherein the SiC is preferably 6H—SiC.

An MIS capacitor with low leakage and high capacitance is disclosed. A layer of hemispherical grained polysilicon (HSG) is formed as a lower electrode. Prior to the dielectric formation, the hemispherical grained polysilicon layer may be optionally subjected to a nitridization or anneal process. A dielectric layer of aluminum oxide (Al2O3), or a composite stack of interleaved layers of aluminum oxide and other metal oxide dielectric materials, is fabricated over the hemispherical grained polysilicon layer and after the optional nitridization or anneal process. The dielectric layer of aluminum oxide (Al2O3) or the aluminum oxide composite stack may be optionally subjected to a post-deposition treatment to further increase the capacitance and decrease the leakage current. A metal nitride upper electrode is formed over the dielectric layer or the composite stack by a deposition technique or by atomic layer deposition.

Disclosed is a method for forming metal oxide dielectric layers, more particularly HfO2 dielectric layers, using an atomic layer deposition (ALD) method in which a series of thin intermediate layers are formed and treated with one or more oxidizers and nitrogents before the next intermediate layer is formed on the substrate. The intermediate oxidation treatments reduce the number of organic contaminants incorporated into the metal oxide layer from the organometallic precursors to produce a dielectric layer having improved current leakage characteristics. The dielectric layers formed in this manner remain susceptible to crystallization if exposed to temperatures much above 550° C., so subsequent semiconductor manufacturing processes should be modified or eliminated to avoid such temperatures or limit the duration at such temperatures to maintain the performance of the dielectric materials.

The present disclosure provides integrated circuit elements and MIM / MIS capacitors having high capacitance and methods of forming according integrated circuit elements and integrated MIM / MIS capacitors and methods of controlling an integrated circuit element and an integrated MIM / MIS capacitor. In various aspects, a substrate is provided and a dielectric layer or insulating layer is formed over the substrate. Furthermore, an electrode layer is disposed over the dielectric layer or insulating layer. Herein, the dielectric layer or insulating layer is in an antiferroelectric phase. In various illustrative embodiments, the integrated circuit element may implement a MOSFET structure or a capacitor structure.

A semiconductor device comprises varactor regions Va and transistor regions Tr. An active region for a varactor is formed with a substrate contact impurity diffusion region obtained by doping an N well region with N-type impurity at a relatively high concentration. However, any extension region (or LDD region) as in a varactor of a known semiconductor device is not formed in the active region for a varactor. On the other hand, parts of a P well region located to both sides of the polysilicon gate electrode in the transistor region Tr are formed with high-concentration source / drain regions and extension regions. Therefore, the extendable range of a depletion layer is kept wide to extend the capacitance variable range of the varactor.

It is an object of the present invention to provide a semiconductor device in which an arrangement area of capacitance can be reduced and resonance frequency can be easily adjusted. The semiconductor device includes an antenna and a resonance circuit including a capacitor connected to the antenna in parallel where the capacitor is formed by connecting x pieces of first capacitor (x is an arbitrary natural number), y pieces of second capacitor (y is an arbitrary natural number), and z pieces of third capacitor (z is an arbitrary natural number) in parallel; and the first capacitor, the second capacitor, and the third capacitor have different capacitance values from each other. It is preferable that each of the first capacitor, the second capacitor, and the third capacitor be a MIS capacitor. Further, at least one of the first capacitor, the second capacitor, and the third capacitor is preferably formed by connecting a plurality of capacitors in parallel.

The invention provides a manufacturing process of a low electromagnetic interference power device terminal structure. The terminal structure manufactured by the process comprises a metallized drain electrode, a first conductive type semiconductor substrate and a first conductive type semiconductor epitaxial layer, a second conductive type semiconductor main junction, a second conductive type semiconductor equipotential ring, a first conductive type cut-off ring, a second conductive type semiconductor field limiting ring, a first dielectric layer, a second dielectric layer, a third dielectric layer, a conductive field plate, a resistor and a metallized source electrode which are stacked from bottom to top. In the invention, an HK dielectric layer can be introduced between the field limitingring and the field plate. An MIS capacitor structure is formed by the semiconductor field limiting ring, the HK dielectric layer and the field plate and is connected in series with an adjacent polycrystalline silicon resistor so that an RC absorption network is formed between high potentials of the source electrode and the drain electrode, dv / dt and di / dt generated by a power device in a fast switch can be effectively inhibited, and an EMI noise is relieved.

The invention relates to a metal insulator semiconductor (MIS) capacitor lower piezoresistance structure adopting a substrate grid and an automatic alignment processing technology for implementing the piezoresistance structure. The structure is used for detecting the displacement of a nano beam. According to the structure, the nano beam is made of top silicon of a silicon on insulator (SOI) chip,a silicon substrate is used as the grid, a silicon dioxide buried layer between the beam and the silicon substrate is removed by corroding to form a clearance, and the silicon substrate, the clearance and the nano beam form the MIS capacitor structure. A voltage is applied to the substrate grid so that a strong inversion layer is formed on the lower surface of the nano beam, and the inversion layer and the silicon above a space charge region are used as piezoresistors to realize piezoresistance detection of vibration of the nano beam. Automatic alignment of a light doped region on the beam and the substrate grid can be realized by combining a composite mask and corrosion of an anisotropic wet method.

The present invention provides a MIS capacitor and a production method of MIS capacitor. A silicon wafer, with a diffusion area formed in a predetermined region on one side, comprises a lower electrode of a capacitor unit. A first metal layer is connected to a first power supply wiring (VDD) and comprises an upper electrode of the capacitor unit. Second metal layers are connected to a second power supply wiring (GND) and are also formed on the side where diffusion area is formed on silicon wafer. An oxide film is placed between the first metal layer and the surface of the silicon wafer where the diffusion area is formed.

An MIM capacitor or an MIS capacitor in semiconductor devices is formed of a thin dielectric layer having a total film thickness less than 100-nm and including a high-dielectric-constant amorphous insulating film, high-breakdown-voltage amorphous films such as of SiO2, and high-dielectric-constant amorphous buffer films between an upper electrode and a lower electrode. The thin high-dielectric-constant amorphous insulation film is formed of a material having a property resistant to fracture although having properties of a large leakage current and a low breakdown voltage, to enhance reliability of the thin dielectric layer and to reduce the footprint thereof in the semiconductor device.

An integrated MIS capacitor structure has a bottom electrode, a capacitor dielectric overlying the bottom electrode, and a plurality of capacitor top plates overlying the capacitor dielectric. In one form each capacitor top plate has a principal dimension and a lesser dimension, wherein individual capacitor top plates of the plurality are arranged proximate and adjacent to one another in an array along respective principal dimensions thereof. The bottom electrode is shared among the plurality of capacitor top plates. At least one of a plurality of conductive stripes is positioned on opposite sides of each capacitor top plate along the principal dimension of a respective capacitor top plate. The structure also has a grounded top metal layer and an inter-level dielectric. An external ground via is disposed adjacent at least one side edge of the plurality of capacitor top plates.

An MIS capacitor with low leakage and high capacitance is disclosed. A layer of hemispherical grained polysilicon (HSG) is formed as a lower electrode. Prior to the dielectric formation, the hemispherical grained polysilicon layer may be optionally subjected to a nitridization or anneal process. A dielectric layer of aluminum oxide (Al2O3), or a composite stack of interleaved layers of aluminum oxide and other metal oxide dielectric materials, is fabricated over the hemispherical grained polysilicon layer and after the optional nitridization or anneal process. The dielectric layer of aluminum oxide (Al2O3) or the aluminum oxide composite stack may be optionally subjected to a post-deposition treatment to further increase the capacitance and decrease the leakage current. A metal nitride upper electrode is formed over the dielectric layer or the composite stack by a deposition technique or by atomic layer deposition.

The invention discloses a manufacturing method of an MIS capacitor with the capacitance being variable, which comprises the steps of 1) growing an N-type lightly doped epitaxy on an N-type heavily doped substrate; 2) growing a sacrificial oxidation layer; 3) defining an N-type ion implantation region and vertically implanting N-type ions; 4) implanting the N-type ions by an oblique angle; 5) removing a photoresist and carrying out thermal annealing; 6) removing the sacrificial oxidation layer and further depositing an oxidation layer; and 7) depositing a metal layer. The invention further discloses a structure of the MIS capacitor. A transverse wave-shaped concentration gradient of the implanted ions is formed in an N-type lightly doped epitaxial layer of the MIS capacitor through the vertical N-type ion implantation and the angled N-type ion implantation and diffusion after implantation. The structure enables the capacitance of the MIS capacitor to be increased along with increase in impressed voltage, the capacitance forms complementation with output capacitance of an RFLDMOS, and the nonlinearity of the output capacitance along with voltage can be reduced through parallel connection and internal matching of the MIS capacitor and the output capacitance of the RFLDMOS.